NQE7520MC S L7RD Intel, NQE7520MC S L7RD Datasheet - Page 14

• Manufacturer Part Number: NQE7520MC S L7RD
• Manufacturer: Intel

Specifications of NQE7520MC S L7RD

• Lead Free Status / RoHS Status: Compliant

Errata
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Implication:
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14
HiLoCS bit not readable in memory error address registers
In memory mirror mode, the Error Address registers utilize bit 0 to signal if the error occurred on
the primary or mirror copy. In the MCH, these bits are not accessible via software and will always
return 0b if read.The affected registers are:
It is not possible to determine which of two DIMMs incurred an SEC or DED error with memory
mirroring enabled.
Refer to your Intel Representative for workaround details.
For the steppings effected, see the Summary Table of Changes.
MCH transitions from Polling.Active prematurely
During a standard link training sequence, the MCH should remain in Polling.Active until TS1
ordered sets with link and lane set to PAD are received on all lanes that passed Receiver Detect.
Because the MCH does not explicitly check for PAD on the link and lane numbers, it is possible for
the MCH to transition from Polling.Active to Polling.Config when a downstream device is not
executing a standard link training sequence (i.e. when the downstream device is actually in
recovery or reset).
This early transition to Polling.Config may result in a degraded link width (e.g. a x4 port may train
as x1), but the link will train.
None required.
For the steppings effected, see the Summary Table of Changes.
Non-fatal completion timeout errors observed on PCI Express devices
When PCI configuration accesses are made on secondary buses to MCH PCI Express bridges
(Device 2-7, Function 0), non-fatal completion timeout errors (EXP_UNCERRSTS, Device 2-7,
Function 0, Offset 104h bit 14) may be observed in the MCH. This condition also applies to PCI
configuration accesses on any downstream device that is in the hot reset state or is disabled.
The system may escalate non-fatal PCI Express completion timeout errors inadvertently.
There are two viable workarounds:
For the steppings effected, see the Summary Table of Changes.
1. Mask the completion timeout errors on MCH PCI Express bridge devices with unpopulated
2. Construct a completion timeout handler to clear the error and return if the Present Detect State
slots as identified by the Present Detect State bit (EXP_SLTSTS, Device 2-7, Function 0,
Offset 7Eh bit 6) in the PCI Express Slot Status register. If a device is present but disabled or in
the hot reset state then the L ink Active bit (VS_STS1, Device 2-7, Function 0, Offset 47h bit
1) should be verified for link status.
bit and the Link Active bit are clear.
DRAM_SCRB_ADD
DRAM_RETR_ADD
DRAM_SEC1_ADD
DRAM_SEC2_ADD
DRAM_DED_ADD
Register
Intel
Device:Function:Offset
®
D0:F1:AC-AFh
D0:F1:C8-CBh
D0:F1:A8-ABh
D0:F1:A0-A3h
D0:F1:A4-A7h
E7520 Memory Controller Hub (MCH) Specification Update