NQE7520MC S L7RD Intel, NQE7520MC S L7RD Datasheet - Page 12

• Manufacturer Part Number: NQE7520MC S L7RD
• Manufacturer: Intel

Specifications of NQE7520MC S L7RD

• Lead Free Status / RoHS Status: Compliant

Errata
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PCI Express link training failures on hot reset
When issuing a hot reset via the bridge control register (BCTRL, Bus 0, Device 2-7, Function 0,
Offset 3Eh bit 6, 1b) secondary bus reset bit to a PCI Express slot, the link may fall back degraded
to a lower link width.
The link may degrade in width or fail to train all together after a hot reset.
Implement a software algorithm that issues a Secondary Bus Reset upon a link training failure for
2 ms. The algorithm should support at least three iterations of Secondary Bus Resets.
For the steppings effected, see the Summary Table of Changes.
Subsystem Identification and Subsystem Vendor Identification register
issue
The Subsystem Vendor Identification register (SVID, Bus 0, D0:F0/F1, D1:F0, D2:F0 & D8:F0,
Offset 2C-2Dh) and the Subsystem Identification register (SID, Bus 0, D0:F0/F1, D1:F0, D2:F0 &
D8:F0, Offset 2E-2Fh) are not able to be written to independently. Writing to one register causes
both to become Read Only.
If the values written to these two registers are not written via the Dword address, then the second
value written will not be set.
Write to both registers at the same time using PCI configuration Dword writes.
For the steppings effected, see the Summary Table of Changes.
MCH responds with illegal access on the Hub Interface for 32 GB
configurations
When devices behind the ICH try to access a memory address above 4 GB in systems with 32 GB
of physical memory, an illegal access error is incorrectly flagged by the MCH.
A spurious error is flagged, and accesses between 4 GB and 32 GB will not succeed in the 32 GB
(maximum) memory configuration, which can result in a system hang.
Refer to your Intel representative for details the Intel
Controller Hub (MCH) Components BIOS Specification for details.
For the steppings effected, see the Summary Table of Changes.
MCH hang on PCI Express enhanced configurations to non-existent devices
causes hang
A system hang may occur when writing or reading to offsets above 0x0FF using the PCI Express
enhanced configuration space of a non-existent device.
An invalid access error will be flagged, and a system hang may result.
Polling or testing for devices must be done using offsets below 0x0FF. Access must not be issued
to offsets above 0x0FF unless the targeted device is confirmed present.
For the steppings effected, see the Summary Table of Changes.
Spurious errors logged during link training events
The MCH reports spurious receiver errors during initial link training, after a retrain, or after a
secondary bus reset has occurred.
Spurious receiver errors will be logged in the associated port. There are no negative side effects
besides the misreported error.
Intel
®
E7520 Memory Controller Hub (MCH) Specification Update
®
E7520, E7320, and E7525 Memory