FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 391
FW82801DB S L66K
Manufacturer Part Number
FW82801DB S L66K
Description
Manufacturer
Intel
Datasheet
1.FW82801DB_S_L66K.pdf
(587 pages)
Specifications of FW82801DB S L66K
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®
82801DB ICH4 Datasheet
11:10
Bit
9:8
7
6
5
4
3
2
1
0
Reserved
Recovery Time (RCT) — R/W. The setting of these bits determines the minimum number of PCI
clocks between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clock
Drive 1 DMA Timing Enable (DTE1) — R/W.
0 = Disable.
1 = Enable the fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data
Drive 1 Prefetch/Posting Enable (PPE1) — R/W.
0 = Disable.
1 = Enable Prefetch and posting to the IDE data port for this drive.
Drive 1 IORDY Sample Point Enable (IE1) — R/W.
0 = Disable IORDY sampling for this drive.
1 = Enable IORDY sampling for this drive.
Drive 1 Fast Timing Bank (TIME1) — R/W.
0 = Accesses to the data port will use compatible timings for this drive.
1 = When this bit =1 and bit 14 = 0, accesses to the data port will use bits 13:12 for the IORDY
Drive 0 DMA Timing Enable (DTE0) — R/W.
0 = Disable
1 = Enable fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data
Drive 0 Prefetch/Posting Enable (PPE0) — R/W.
0 = Disable prefetch and posting to the IDE data port for this drive.
1 = Enable prefetch and posting to the IDE data port for this drive.
Drive 0 IORDY Sample Point Enable (IE0) — R/W.
0 = Disable IORDY sampling is disabled for this drive.
1 = Enable IORDY sampling for this drive.
Drive 0 Fast Timing Bank (TIME0) — R/W.
0 = Accesses to the data port will use compatible timings for this drive.
1 = Accesses to the data port will use bits 13:12 for the IORDY sample point, and bits 9:8 for the
port will run in compatible timing.
sample point, and bits 9:8 for the recovery time. When this bit = 1 and bit 14 = 1, accesses to
the data port will use the IORDY sample point and recover time specified in the slave IDE
timing register.
port will run in compatible timing.
recovery time.
Description
IDE Controller Registers (D31:F1)
391
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