FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 465

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

13.2.18
13.2.19
Intel
®
82801DB ICH4 Datasheet
Note: This register is in the resume well and is reset by RSMRST#
Note: This register is in the resume well and is reset by RSMRST#
NOTIFY_DLOW—Notify Data Low Byte Register
Register Offset:
Default Value:
NOTIFY_DHIGH—Notify Data High Byte Register
Register Offset:
Default Value:
Bit
7:0
Bit
7:0
DATA_LOW_BYTE — RO. This field contains the first (low) byte of data received during the Host
Notify protocol of the SMBus 2.0 Specification. Software should only consider this field valid when the
HOST_NOTIFY_STS bit is set to 1.
DATA_HIGH_BYTE — RO. This field contains the second (high) byte of data received during the Host
Notify protocol of the SMBus 2.0 Specification. Software should only consider this field valid when the
HOST_NOTIFY_STS bit is set to 1.
16h
00h
17h
00h
Description
Description
Attribute:
Size:
Attribute:
Size:
SMBus Controller Registers (D31:F3)
RO
8 bits
RO
8 bits
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