M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 58

• Manufacturer Part Number: M66291GP#201
• Description: IC USB CONTROLLER GEN-PUR 48LQFP
• Manufacturer: Renesas Electronics America

Specifications of M66291GP#201

• Package / Case: 48-LQFP
• Mounting Type: Surface Mount
• Current - Supply: 30mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Interface: Serial
• Controller Type: USB 2.0 Controller
• Lead Free Status / RoHS Status: Not Compliant

M 6 6 2 9 1 G P / H P
R e v 1 . 0 1
(3) BCLR (Buffer Clear) Bit (b12)
(4) Creq (CPU_FIFO Ready) Bit (b11)
This bit clears the data written to the CPU side buffer.
This bit automatically returns to “0” after the buffer is cleared.
When this bit is equal to “1”, this bit indicates the states as follows:
Make sure that this bit is equal to “0” before accessing the aforesaid registers/bits.
2 0 0 4 . 1 1 . 0 1
Note:
When set to IN buffer (EPi_DIR bit = “1”)
When set to OUT buffer (EPi_DIR bit = “0”)
When set to IN buffer (EPi_DIR bit = “1”)
When this bit is set to “0”, the CPU side buffer is ready to write the transmit data.
This bit is cleared to “0” due to one of the reasons as follows:
The transmit completion is changed by the EPi_RWMD bit.
This bit is set to “1” due to one of the reasons as follows:
The write completion also is changed by the EPi_RWMD bit.
When the IVAL bit is set to “1”, the following operations are executed by writing “1” to this bit:
When the IVAL bit is set to “0”, the following operations are executed by writing “1” to this bit:
Further, the zero-length packet can be transmitted by writing “1” simultaneously to this bit and to the
IVAL bit. For details, refer to “IVAL bit”.
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Refer to “3.2 FIFO Buffer” for CPU/SIE side.
When set to single buffer mode (EPi_DBLB bit = “0”)
CPU_FIFO Data Register can not be accessed.
The IVAL bit value of this register is invalid.
The CPU_DTLN bit values of this register are invalid.
When set to double buffer mode (EPi_DBLB bit = “1”)
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p a g e 5 8 o f 1 2 2
Completes transmitting of SIE side buffer.
Writes “1” to the SCLR bit.
Writes “1” to the ACLR bit.
Completes transmitting of SIE side buffer and writing of CPU side buffer.
Writes “1” to the SCLR bit.
Writes “1” to the ACLR bit.
Writes “1” to the BCLR bit.
Completes writing the transmit data to CPU side buffer.
Writes “1” to this bit.
When “1” is written to this bit, the write operation is forcibly completed. When some written
data exists in the buffer, that data is solely transmitted as the short packet. Here, if the
buffer is empty or cleared, the zero-length packet is transmitted. The buffer can be cleared
using the BCLR bit. Further, the zero-length packet can be transmitted by writing “1”
simultaneously to this bit and to the BCLR bit. In this case the buffer is cleared by setting “1”
to BCLR bit, and this bit is cleared to “0” after the zero-length packet is transmitted.
Clears CPU side buffer.
Clears the IVAL bit of this register.
Clears the CPU_DTLN bits of this register.
Clears CPU side buffer.