M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 78

• Manufacturer Part Number: M66291GP#201
• Description: IC USB CONTROLLER GEN-PUR 48LQFP
• Manufacturer: Renesas Electronics America

Specifications of M66291GP#201

• Package / Case: 48-LQFP
• Mounting Type: Surface Mount
• Current - Supply: 30mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Interface: Serial
• Controller Type: USB 2.0 Controller
• Lead Free Status / RoHS Status: Not Compliant

M 6 6 2 9 1 G P / H P
R e v 1 . 0 1
(6) EPi_RWMD (Continuous Transmit/Receive Mode) Bit (b6)
(7) EPi_Buf_Nmb (Buffer Start Number) Bits (b5~b0)
This bit sets the transmit/receive mode at bulk transfer.
This bit can be set to “1” only when the transfer type is set to bulk transfer (EPi_TYP bits = “01”).
Set to “0” for other transfer modes.
The set/clear conditions of the IVAL bit change according to this bit.
These bits set the beginning block number of the buffer.
The block number is a number by dividing the FIFO buffer into 64 byte sections (Note 1).
The domain set by the EPi_Buf_siz bit from the block set by these bits is secured as the buffer (Note 2).
2 0 0 4 . 1 1 . 0 1
Note 1: The M66291 is equipped with 3 Kbytes FIFO buffer and has the blocks from H’0 to H’2F.
Note 2: Make sure that several endpoints may not get overlapped in the same buffer area.
When set to OUT buffer (EPi_DIR bit = “0”)
When set to IN buffer (EPi_DIR bit = “1”)
In case of single transmit/receive mode, the receive completes after receiving one packet under the
conditions as follows:
In case of continuous transmit/receive mode, the receive completes after receiving several packets
under the conditions as follows:
In case of single transmit/receive mode, the transmit completes after transmitting one packet under
the conditions as follows:
In case of continuous transmit/receive mode, the transmit completes after transmitting several packets
under the conditions as follows:
In case of single transmit/receive mode, the write completes under the conditions as follows:
In case of continuous transmit/receive mode, the write completes under the conditions as follows:
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p a g e 7 8 o f 1 2 2
Receives the data equivalent to the size set by the EPi_MXPS bits.
Receives the short packet (including the zero-length packet).
Receives automatically the data equivalent to the size set by the EPi_MXPS bits several
times and receives the data equivalent to the byte set by the EPi_Buf_siz bit.
Receives the short packet (including the zero-length packet).
When the value set by the DMAn_Transaction Count Register conforms to the packet
receiving count.
Transmits the data equivalent to the size set by the EPi_MXPS bits or the zero-length
packet.
Transmits automatically the data equivalent to the size set by the EPi_MXPS bits several
times and transmits the data equivalent to the byte set by the EPi_Buf_siz bit.
Writes the data equivalent to the size set by the EPi_MXPS bits to the buffer (IVAL bit
changed to “1”).
Writes “1” to the IVAL bit of the CPU_FIFO Control/Dn_FIFO Control Register.
Writes the data equivalent to the size set by the EPi_Buf_siz bit to the buffer (IVAL bit
changed to “1”).
Writes “1” to the IVAL bit.