M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 87

• Manufacturer Part Number: M66291GP#201
• Description: IC USB CONTROLLER GEN-PUR 48LQFP
• Manufacturer: Renesas Electronics America

Specifications of M66291GP#201

• Package / Case: 48-LQFP
• Mounting Type: Surface Mount
• Current - Supply: 30mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Interface: Serial
• Controller Type: USB 2.0 Controller
• Lead Free Status / RoHS Status: Not Compliant

M 6 6 2 9 1 G P / H P
3.3 USB Data Transfer Function Overview
3.3.1
3.3.2
3.3.3
R e v 1 . 0 1
Data Receive Function
Data Transmit Function
Data Transfer Sequence
b0
The M66291 is capable of executing the USB transfer by processing the operations as follows:
1
The data receiving operation of the setup transaction and the OUT transaction differs as follows.
The data transmit is executed on receiving the request for data transmit by the IN token packet.
The data written to the FIFO Data Register are transmitted to the USB bus in the order of LSB first. The
same is true when the data received from the USB bus is stored to the FIFO Data Register.
2 0 0 4 . 1 1 . 0 1
(1) Response against the control transfer request
(2) Enable of transmitting after storing the transmit data to the buffer
(3) Stall processing
(4) Suspend/resume processing
Setup transaction (control transfer setup stage)
OUT transaction
IN transaction
b1
Enable of receiving and reading the receive data from the buffer
The device request data received from the host (8 bytes) are stored to 4 different registers.
Here, ACK response is executed to the host and the control transfer stage transition interrupt has
occurred.
In the data packet after receiving OUT token from the host, when the buffer receives the packet of
maximum size or the short packet, the ACK response is executed to the host and the buffer ready
interrupt has occurred (ready for reading the receive data).
When the buffer is not in the receive ready state, the buffer not ready interrupt has occurred.
After the IN token is received from the host, the buffer data is transmitted. On completion of the buffer
data transmit, the buffer ready interrupt has occurred (ready for writing the transmit data).
When the buffer is not in transmit ready state, the buffer not ready interrupt has occurred.
b2
p a g e 8 7 o f 1 2 2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
b13
b14
b15
16