PSD813F2-A-70J STMicroelectronics, PSD813F2-A-70J Datasheet - Page 21

• Manufacturer Part Number: PSD813F2-A-70J
• Manufacturer: STMicroelectronics

Specifications of PSD813F2-A-70J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

PSD8XXFX
3.4
3.5
3.6
3.7
3.8
I/O ports
The PSD has 27 individually configurable I/O pins distributed over the four ports (Port A, B,
C, and D). Each I/O pin can be individually configured for different functions. ports can be
configured as standard MCU I/O ports, PLD I/O, or latched address outputs for MCUs using
multiplexed address/data buses.
The JTAG pins can be enabled on port C for in-system programming (ISP).
Ports A and B can also be configured as a data port for a non-multiplexed bus.
MCU bus interface
PSD interfaces easily with most 8-bit MCUs that have either multiplexed or non-multiplexed
address/data buses. The device is configured to respond to the MCU control signals, which
are also used as inputs to the PLDs. For examples, please see
interface
Table 4.
JTAG port
In-system programming (ISP) can be performed through the JTAG signals on port C. This
serial interface allows complete programming of the entire PSD device. A blank device can
be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can
be multiplexed with other functions on port C.
In-system programming (ISP)
Using the JTAG signals on port C, the entire PSD device can be programmed or erased
without the use of the MCU. The primary Flash memory can also be programmed in-system
by the MCU executing the programming algorithms out of the secondary memory, or SRAM.
The secondary memory can be programmed the same way by executing out of the primary
Flash memory. The PLD or other PSD configuration blocks can be programmed through the
JTAG port or a device programmer.
program different functional blocks of the PSD.
Power management unit (PMU)
The power management unit (PMU) gives the user control of the power consumption on
selected functional blocks based on system requirements. The PMU includes an Automatic
Power-down (APD) Unit that turns off device functions during MCU inactivity. The APD unit
has a Power-down mode that helps reduce power consumption.
Decode PLD (DPLD)
Complex PLD (CPLD)
examples.
PLD I/O
Name
Doc ID 7833 Rev 7
Table 6
73
73
indicates which programming methods can
Inputs
Table 5
indicates the JTAG pin assignments.
17
19
Outputs
PSD architectural overview
Section 15.4: MCU bus
42
140
Product terms
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