PSD813F2-A-70J STMicroelectronics, PSD813F2-A-70J Datasheet - Page 41
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PSD813F2-A-70J
Manufacturer Part Number
PSD813F2-A-70J
Description
Manufacturer
STMicroelectronics
Datasheet
1.PSD813F2-A-70J.pdf
(128 pages)
Specifications of PSD813F2-A-70J
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Package Type
PLCC
Mounting
Surface Mount
Pin Count
52
Lead Free Status / RoHS Status
Compliant
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PSD8XXFX
10.3
Reset (RESET) signal (on the PSD83xF2 and PSD85xF2)
A pulse on Reset (RESET) aborts any cycle that is in progress, and resets the Flash
memory to the READ mode. When the reset occurs during a program or erase cycle, the
Flash memory takes up to 25μs to return to the READ mode. It is recommended that the
Reset (RESET) pulse (except for Power On Reset, as described in
and device status at
the MCU to fetch the bootstrap instructions after the Reset cycle is complete.
Table 12.
1. Bit Definitions:
Table 13.
1. Bit Definitions:
Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Security_B
it
Sec<i>_Prot 1 = Primary Flash memory or secondary Flash memory Sector <i> is write protected.
Sec<i>_Prot 0 = Primary Flash memory or secondary Flash memory Sector <i> is not write protected.
Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write protected.
Sec<i>_Prot 0 = Secondary Flash memory Sector <i> is not write protected.
Security_Bit 0 = Security Bit in device has not been set.
1 = Security Bit in device has been set.
Bit 7
Bit 7
not used
Sector Protection/Security Bit definition – Flash Protection register
Sector Protection/Security Bit definition – PSD/EE Protection register
Bit 6
Bit 6
reset) be at least 25 µs so that the Flash memory is always ready for
not used
Bit 5
Bit 5
Doc ID 7833 Rev 7
not used
Bit 4
Bit 4
Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Bit 3
Bit 3
Bit 2
Bit 2
Section 18: Reset timing
Bit 1
Bit 1
Specific features
Bit 0
Bit 0
(1)
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