PSD813F2-A-70J STMicroelectronics, PSD813F2-A-70J Datasheet - Page 51

• Manufacturer Part Number: PSD813F2-A-70J
• Manufacturer: STMicroelectronics

Specifications of PSD813F2-A-70J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

PSD8XXFX
14.3
Complex PLD (CPLD)
The CPLD can be used to implement system logic functions, such as loadable counters and
shift registers, system mailboxes, handshaking protocols, state machines, and random logic.
The CPLD can also be used to generate three External Chip Select (ECS0-ECS2), routed to
port D.
Although External Chip Select (ECS0-ECS2) can be produced by any Output macrocell
(OMC), these three External Chip Select (ECS0-ECS2) on port D do not consume any
Output macrocells (OMC).
As shown in
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Each of the blocks are described in the sections that follow.
The input macrocells (IMC) and Output macrocells (OMC) are connected to the PSD
internal data bus and can be directly accessed by the MCU. This enables the MCU software
to load data into the Output macrocells (OMC) or read data from both the input and Output
macrocells (IMC and OMC).
This feature allows efficient implementation of system logic and eliminates the need to
connect the data bus to the AND Array as required in most standard PLD macrocell
architectures.
24 input macrocells (IMC)
16 Output macrocells (OMC)
Macrocell Allocator
Product Term Allocator
AND Array capable of generating up to 137 product terms
Four I/O ports.
Figure
12, the CPLD has the following blocks:
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PLDS