PSD813F2-A-70J STMicroelectronics, PSD813F2-A-70J Datasheet - Page 86

• Manufacturer Part Number: PSD813F2-A-70J
• Manufacturer: STMicroelectronics

Specifications of PSD813F2-A-70J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

Reset timing and device status at reset
Figure 33. Reset (RESET) timing
Table 34.
1. The SR_cod and Periphmode bits in the VM register are always cleared to '0' on Power-on reset or Warm reset.
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MCU I/O
PLD Output
Address Out
Data port
Peripheral I/O
PMMR0 and PMMR2
Macrocells flip-flop status
VM register
All other registers
Port configuration
V
RESET
CC
Register
(1)
Status during Power-on reset, Warm reset and Power-down mode
Power-On Reset
V
t NLNH-PO
CC
(min)
Input mode
Valid after internal PSD
configuration bits are
loaded
Tri-stated
Tri-stated
Tri-stated
Cleared to '0'
Cleared to '0' by internal
Power-On Reset
Initialized, based on the
selection in PSDsoft
Configuration menu
Cleared to '0'
Power-on reset
Power-on reset
t OPR
Doc ID 7833 Rev 7
Input mode
Valid
Tri-stated
Tri-stated
Tri-stated
Unchanged
Depends on .re and .pr
equations
Initialized, based on the
selection in PSDsoft
Configuration menu
Cleared to '0'
Warm reset
Warm reset
Warm Reset
t NLNH-A
t NLNH
Unchanged
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Not defined
Tri-stated
Tri-stated
Unchanged
Depends on .re and .pr
equations
Unchanged
Unchanged
Power-down mode
Power-down mode
t OPR
PSD8XXFX
AI02866b