LSISAS1064 LSI, LSISAS1064 Datasheet - Page 108

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

4-40
31
1
1
1
1
1
1
1
Table 4.9
Register: 0x40
Request Queue
Read/Write
The Request Queue accepts Request Post MFAs from the host system
on writes.
PCI Host Register Description
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Bits [9:8] Encodings Interrupt Signal Routing
0b00
0b01
0b10
0b11
24 23
1
1
1
1
1
Interrupt Signal Routing
Reserved
This field is reserved.
Reply Interrupt Mask
Setting this bit masks reply interrupts and prevents the
assertion of a PCI interrupt for all reply interrupt conditions.
Reserved
This field is reserved.
Doorbell Interrupt Mask
Setting this bit masks System Doorbell interrupts and
prevents the assertion of a PCI interrupt for all System
Doorbell interrupt conditions.
Request Queue
For reads, this register contains 0xFFFFFFFF. For writes,
the register contains the Request Post MFA.
1
1
Request Queue
1
INTA/ and ALT_INTA/
INTA/ Only
ALT_INTA/ Only
INTA/ and ALT_INTA/
16 15
1
1
1
1
1
1
1
1
8
1
7
1
1
1
1
1
1
[31:0]
1
[7:4]
[2:1]
0
1
3
0