LSISAS1064 LSI, LSISAS1064 Datasheet - Page 40

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

2.3.2.14
2.3.2.15
2.3.2.16
2.3.2.17
2-14
Dual Address Cycles (DAC) Command
Memory Read Line Command
Memory Read Block Command
Memory Write and Invalidate Command
transactions when operating in the PCI-X mode. A split transaction
consists of at least two separate bus transactions: a split request, which
the requester initiates, and one or more split completion commands,
which the completer initiates. Revision 2.0 of the PCI-X addendum
permits split transaction completion for the Memory Read Block, Alias to
Memory Read Block, Memory Read Dword, Interrupt Acknowledge,
I/O Read, I/O Write, Configuration Read, and Configuration Write
commands. When operating in the PCI-X mode, the LSISAS1064
supports the Split Completion command for all of these commands
except the Interrupt Acknowledge command, which the LSISAS1064
neither responds to nor generates.
The LSISAS1064 performs Dual Address Cycles (DAC), per the PCI
Local Bus Specification, Version 3.0. The LSISAS1064 supports this
command when operating in either the PCI or PCI-X bus mode.
This command is identical to the Memory Read command except it
additionally indicates that the master intends to fetch a complete cache
line. The LSISAS1064 supports this command when operating in the PCI
mode.
The LSISAS1064 uses this command to read from memory. The
LSISAS1064 supports this command when operating in the PCI-X mode.
The Memory Write and Invalidate command is identical to the Memory
Write command, except it additionally guarantees a minimum transfer of
one complete cache line. The master uses this command when it intends
to write all bytes within the addressed cache line in a single PCI
transaction unless interrupted by the target. This command requires
implementation of the PCI
determines when to issue a Write and Invalidate command instead of a
Memory Write command and supports this command when operating in
the PCI bus mode.
Functional Description
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Cache Line Size
register. The LSISAS1064