LSISAS1064 LSI, LSISAS1064 Datasheet - Page 23
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LSISAS1064
Manufacturer Part Number
LSISAS1064
Description
Manufacturer
LSI
Datasheet
1.LSISAS1064.pdf
(152 pages)
Specifications of LSISAS1064
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LSISAS1064/62042D2
Manufacturer:
LSILogic
Quantity:
120
Part Number:
LSISAS1064A2
Manufacturer:
LSI
Quantity:
20 000
Company:
Part Number:
LSISAS1064A3
Manufacturer:
LATTICE
Quantity:
628
Part Number:
LSISAS1064A3
Manufacturer:
LSI
Quantity:
20 000
Company:
Part Number:
LSISAS1064E
Manufacturer:
ST
Quantity:
2 241
Company:
Part Number:
LSISAS1064E
Manufacturer:
LSI
Quantity:
996
Part Number:
LSISAS1064E
Manufacturer:
LSI
Quantity:
20 000
Part Number:
LSISAS1064E B1
Manufacturer:
LSILOGI
Quantity:
20 000
Company:
Part Number:
LSISAS1064E B3
Manufacturer:
LSI
Quantity:
59
Part Number:
LSISAS1064E B3
Manufacturer:
LSI
Quantity:
20 000
1.6.4
Integration
These features make the LSISAS1064 easy to integrate:
Summary of LSISAS1064 Features
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
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Provides unequaled performance through the Fusion-MPT
architecture
Provides high throughput and low CPU utilization to off load the host
processor
Uses a dedicated ARM926 processor
Presents a single electrical load to the PCI Bus
Reduces Interrupt Service Routine (ISR) overhead with interrupt
coalescing
Supports Message Signaled Interrupts (MSI) and MSI-X
Supports 32-bit or 64-bit data bursts with variable burst lengths
Supports the PCI Cache Line Size register
Supports the PCI Memory Write and Invalidate, Memory Read Line,
and Memory Read Multiple commands
Supports the PCI-X Memory Read Dword, Split Completion, Memory
Read Block, Memory Write Block commands
Supports up to 16 PCI-X Split Transaction cycles
Supports backwards compatibility with previous revisions of the PCI
specification, with the exception that the LSISAS1064 does not
support 5 V PCI
Supports 32-bit or 64-bit addressing through Dual Address
Cycles (DAC)
Provides a theoretical 1066 Mbytes/s PCI bandwidth
Supports 3.3 V PCI, and is not 5 V PCI tolerant
Complies with the PCI Local Bus Specification, Revision 3.0
Complies with the PCI-X Addendum to the PCI Local Bus
Specification, Revision 2.0
Complies with the PCI Power Management Interface
Specification, Revision 1.2
Complies with the PC2001 Specification
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