LSISAS1064 LSI, LSISAS1064 Datasheet - Page 73

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

Register: 0x06–0x07
Status
Read/Write
Reads to this register behave normally. To clear a bit location that is
currently set, write the bit to one (1). For example, to clear bit 15 when
it is set and not affect any other bits, write 0x8000 to the register.
PCI Configuration Space Register Description
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
15
0
0
0
Enable Memory Space
This bit controls the ability of the PCI function to respond
to Memory Space accesses. Setting this bit allows the
LSISAS1064 to respond to Memory Space accesses at
the address range specified by the
Memory [0]
the
this bit disables the PCI function’s response to PCI Mem-
ory Space accesses.
Enable I/O Space
This bit controls the LSISAS1064 PCI function’s response
to I/O Space accesses. Setting this bit enables the PCI
function to respond to I/O Space accesses at the address
range the PCI Configuration Space
register specifies. Clearing this bit disables the PCI
function’s response to I/O Space accesses.
0
Detected Parity Error (from Slave)
This bit is set per the PCI Local Bus Specification,
Version 3.0, and PCI-X Addendum to the PCI Local Bus
Specification, Revision 2.0.
Signaled System Error
The LSISAS1064 PCI function sets this bit when
asserting the SERR/ signal.
Received Master Abort (from Master)
A master device sets this bit when a Master Abort
command terminates its transaction (except for Special
Cycle).
Expansion ROM Base Address
0
0
High,
1
Memory [1]
8
0
Status
7
0
0
Low,
1
Memory [1]
Memory [0]
registers. Clearing
I/O Base Address
1
0
0
High, and
Low,
0
4-5
0
0
15
14
13
1
0