LSISAS1064 LSI, LSISAS1064 Datasheet - Page 85
LSISAS1064
Manufacturer Part Number
LSISAS1064
Description
Manufacturer
LSI
Datasheet
1.LSISAS1064.pdf
(152 pages)
Specifications of LSISAS1064
Lead Free Status / RoHS Status
Not Compliant
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Register: 0xXX
Power Management Capability ID
Read Only
Register: 0xXX
Power Management Next Pointer
Read Only
Register: 0xXX
Power Management Capabilities
Read Only
PCI Configuration Space Register Description
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
15
0
7
0
7
x
0
0
0
x
0
Max_Lat
This register specifies the desired settings for the latency
timer values in units of 0.25 s. Max_Lat specifies how
often the device needs to gain access to the PCI bus.
The LSISAS1064 sets this register to 0x0A since it
requires the PCI bus every 2.5 s.
Power Management Capability ID
This register indicates the type of the current data
structure. It is set to 0x01 to indicate the Power
Management Data Structure.
Power Management Next Pointer
This register contains the pointer to the next item in the
PCI function’s extended capabilities list. The value of this
register varies according to system configuration.
0
0
x
Power Management Capability ID
Power Management Next Pointer
Power Management Capabilities
1
1
0
x
8
0
7
0
0
x
0
0
0
x
0
0
0
x
0
1
0
1
0
x
[7:0]
[7:0]
[7:0]
4-17
0
0