LSISAS1064 LSI, LSISAS1064 Datasheet - Page 41

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

2.3.2.18
2.3.3
2.3.4
PCI Arbitration
PCI Cache Mode
Memory Write Block Command
Alignment – The LSISAS1064 uses the calculated line size value to
determine if the current address aligns to the cache line size. If the
address does not align, the LSISAS1064 bursts data using a noncache
command. If the starting address aligns, the LSISAS1064 issues a
Memory Write and Invalidate command using the cache line size as the
burst size.
Multiple Cache Line Transfers – The Memory Write and Invalidate
command can write multiple cache lines of data in a single bus
ownership. The LSISAS1064 issues a burst transfer as soon as it
reaches a cache line boundary. The PCI Local Bus specification states
that the transfer size must be a multiple of the cache line size. The
LSISAS1064 selects the largest multiple of the cache line size based on
the transfer size. When the DMA buffer contains less data than the value
Cache Line Size
Write command on the next cache boundary to complete the data
transfer.
The LSISAS1064 uses this command to burst data to memory. The
LSISAS1064 supports this command when operating in the PCI-X bus
mode.
The LSISAS1064 contains an independent bus mastering function. The
system interface bus mastering function manages DMA operations as
well as the request and reply message frames.
The LSISAS1064 supports an 8-bit
Line Size
addresses corresponding to cache line boundaries. The LSISAS1064
determines when to issue a PCI cache command (Memory Read Line,
Memory Read Multiple, and Memory Write and Invalidate), or PCI
noncache command (Memory Read or Memory Write command).
PCI Functional Description
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
register provides the ability to sense and react to nonaligned
register specifies, the LSISAS1064 issues a Memory
Cache Line Size
register. The
Cache
2-15