DSP56301VF100 Freescale, DSP56301VF100 Datasheet - Page 121

• Manufacturer Part Number: DSP56301VF100
• Manufacturer: Freescale

Specifications of DSP56301VF100

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 252
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
M_BME EQU 12
M_BRE EQU 13
M_BSTR EQU 14
M_BRF EQU $7F8000; Refresh Rate Bits Mask (BRF0-BRF7)
M_BRP EQU 23
;
M_BAT EQU $3
M_BAAP EQU 2
M_BPEN EQU 3
M_BXEN EQU 4
M_BYEN EQU 5
M_BAM EQU 6
M_BPAC EQU 7
M_BNC EQU $F00
M_BAC EQU $FFF000; Address to Compare Bits Mask (BAC0-BAC11)
;
M_CP EQU $c00000 ; mask for CORE-DMA priority bits in SR
M_CA EQU 0
M_V EQU 1
M_Z EQU 2
M_N EQU 3
M_U EQU 4
M_E EQU 5
M_L EQU 6
M_S EQU 7
M_I0 EQU 8
M_I1 EQU 9
M_S0 EQU 10
M_S1 EQU 11
M_SC EQU 13
M_DM EQU 14
M_LF EQU 15
M_FV EQU 16
M_SA EQU 17
M_CE EQU 19
M_SM EQU 20
M_RM EQU 21
M_CP0 EQU22
M_CP1 EQU 23
;
M_CDP EQU$300 ; mask for CORE-DMA priority bits in OMR
M_MA EQU 0
M_MB EQU 1
M_MC EQU 2
M_MD EQU 3
M_EBD EQU 4
M_SD EQU 6
M_CDP0 EQU 8
M_CDP1 EQU 9
M_BEN EQU 10
M_TAS EQU 11
M_BRT EQU 12
M_XYS EQU 16
M_EUN EQU 17
M_EOV EQU 18
Address Attribute Registers
control and status bits in SR
control and status bits in OMR
; Packing Enable
; Overflow
; Zero
; Negative
; Unnormalized
; Extension
; Limit
; Scaling Bit
; bit 0 of priority bits in SR
; Mastership Enable
; Refresh Enable
; Refresh prescaler
; External Access Type and Pin Definition Bits Mask (BAT0-BAT1)
; Address Muxing
; Number of Address Bits to Compare Mask (BNC0-BNC3)
; Carry
; Interupt Mask Bit 0
; Interupt Mask Bit 1
; Scaling Mode Bit 0
; Scaling Mode Bit 1
; Sixteen_Bit Compatibility
; Double Precision Multiply
; DO-Loop Flag
; DO-Forever Flag
; Sixteen-Bit Arithmetic
; Instruction Cache Enable
; Arithmetic Saturation
; Rounding Mode
; Operating Mode A
; Operating Mode B
; Operating Mode C
; Operating Mode D
; Stop Delay
; Software Triggered Refresh
; Address Attribute Pin Polarity
; Program Space Enable
; X Data Space Enable
; Y Data Space Enable
; bit 1 of priority bits in SR
; External Bus Disable bit in OMR
; Burst Enable
; TA Synchronize Select
; Bus Release Timing
; Stack Extension space select bit in OMR.
; Extensed stack UNderflow flag in OMR.
; Extended stack OVerflow flag in OMR.
; bit 0 of priority bits in OMR
; bit 1 of priority bits in OMR
DSP56301 Technical Data, Rev. 10
A-15