DSP56301VF100 Freescale, DSP56301VF100 Datasheet - Page 13

DSP56301VF100

Manufacturer Part Number
DSP56301VF100
Description
Manufacturer
Freescale
Datasheet

Specifications of DSP56301VF100

Device Core Size
24b
Format
Fixed Point
Clock Freq (max)
100MHz
Mips
100
Device Input Clock Speed
100MHz
Ram Size
24KB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
252
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
DSP56301VF100
Manufacturer:
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Quantity:
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Part Number:
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Manufacturer:
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1.6 Interrupt and Mode Control
The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset. After
RESET
Freescale Semiconductor
MODA
IRQA
MODB
IRQB
MODC
IRQC
Signal Name
is deasserted, these inputs are hardware interrupt request lines.
Input
Input
Input
Input
Input
Input
Type
Input
Input
Input
State During
Table 1-9.
Reset
DSP56301 Technical Data, Rev. 10
Interrupt and Mode Control
Mode Select A
Selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input
IRQA during normal instruction processing. MODA, MODB, MODC, and
MODD select one of sixteen initial chip operating modes, latched into the OMR
when the RESET signal is deasserted.
External Interrupt Request A
Internally synchronized to CLKOUT. If IRQA is asserted synchronous to
CLKOUT, multiple processors can be re-synchronized using the WAIT
instruction and asserting IRQA to exit the Wait state. If the processor is in the
Stop stand-by state and IRQA is asserted, the processor exits the Stop state.
These inputs are 5 V tolerant.
Mode Select B
Selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input
IRQB during normal instruction processing. MODA, MODB, MODC, and
MODD select one of sixteen initial chip operating modes, latched into the OMR
when the RESET signal is deasserted.
External Interrupt Request B
Internally synchronized to CLKOUT. If IRQB is asserted synchronous to
CLKOUT, multiple processors can be re-synchronized using the WAIT
instruction and asserting IRQB to exit the Wait state. If the processor is in the
Stop stand-by state and IRQC is asserted, the processor will exit the Stop
state.
These inputs are 5 V tolerant.
Mode Select C
Selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input
IRQC during normal instruction processing. MODA, MODB, MODC, and
MODD select one of sixteen initial chip operating modes, latched into the OMR
when the RESET signal is deasserted.
External Interrupt Request C
Internally synchronized to CLKOUT. If IRQC is asserted synchronous to
CLKOUT, multiple processors can be re-synchronized using the WAIT
instruction and asserting IRQC to exit the Wait state. If the processor is in the
Stop stand-by state and IRQC is asserted, the processor exits the Stop state.
These inputs are 5 V tolerant.
Signal Description
Interrupt and Mode Control
1-9

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