ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 497

• Manufacturer Part Number: ALXD800EEXJ2VC C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VC C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Video Input Port Register Descriptions
6.10.2.9 VIP Task A VBI Even Base Address (VIP_TASK_A_VBI_EVEN_BASE)
VIP Memory Offset 20h
Type
Reset Value
6.10.2.10 VIP Task A VBI Odd Base Address (VIP_TASK_A_VBI_ODD_BASE)
VIP Memory Offset 24h
Type
Reset Value
AMD Geode™ LX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:0
31:0
Bit
Bit
Name
TASK_A_VBI_E
VEN_BASE
Name
TASK_A_VBI_O
DD_BASE
R/W
00000000h
R/W
00000000h
Description
Task AVBI Even Base Address. This register specifies the base address in graphics
memory where VBI data for even fields is stored. Changes to this register take effect at
the beginning of the next field. The value in this register is 16-byte aligned. This value
needs to be 32-byte aligned. (Bits [4:0] are required to be 00000.)
Note:
Description
Task A VBI Odd Base Address. This register specifies the base address in graphics
memory where Task A VBI data for odd fields are stored. Changes to this register take
effect at the beginning of the next field. The value in this register is 8-byte aligned. This
value needs to be 32-byte aligned. (Bits [4:0] are required to be 00000.)
Note:
VIP_TASK_A_VBI_EVEN_BASE Bit Descriptions
VIP_TASK_A_VBI_ODD_BASE Bit Description
VIP_TASK_A_VBI_EVEN_BASE Register Map
VIP_TASK_A_VBI_ODD_BASE Register Map
TASK_A_VBI_DATA_EVEN_BASE
TASK_A_VBI_DATA_ODD_BASE
This register is double buffered. When a new value is written to this register, the
new value is placed in a special pending register, and the Base Register Not
Updated bit (VIP Memory Offset 08h[16]) is set to 1. The Task A VBI Even Base
Address register is not updated at this point. When the first data of the next field
is captured, the pending values of all base registers are written to the appropriate
base registers, and the Base Register Not Updated bit is cleared.
This register is double buffered. When a new value is written to this register, the
new value is placed in a special pending register, and the Task A Base Register
Not Updated bit (VIP Memory Offset 08h[16]) is set to 1. The Task A VBI Odd
Base Address register is not updated at this point. When the first data of the next
field is captured, the pending values of all base registers are written to the appro-
priate base registers, and the Base Register Not Updated bit is cleared.
9
9
8
8
33234H
7
7
6
6
5
5
4
4
Program to 00000
Program to 00000
3
3
2
2
1
1
497
0
0