ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 80

• Manufacturer Part Number: ALXD800EEXJ2VC C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VC C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

4.2.4
P2D descriptors are ordered P2D_BM, P2D_BMO, P2D_R, P2D_RO, P2D_SC, P2D_BMK. For example if NP2D_BM=3
and NP2D_BM0=2, IMSR EO = P2D_BM[0], MSR E3 = P2D_SC[0].
4.2.4.1
GLIU0
MSR Address
Type
Reset Value
See Table 4.1.3.1 "Memory Routing and Translation" on page 47 for details on the descriptor usage.
80
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:61
59:40
39:20
PDID1
19:0
Bit
60
P2D Descriptor Registers
P2D Base Mask Descriptor (P2D_BM)
Name
PDID1
PCMP_BIZ
RSVD
PBASE
PMASK
PBASE
P2D_BM[5:0]
10000020h-10000025h
R/W
000000FF_FFF00000h
33234H
Description
Descriptor Destination ID. These bits define which Port to route the request to, if it is a
‘hit’ based on the other settings in this register.
000: Port 0 (GLIU0 = GLIU; GLIU1 = GLIU.)
001: Port 1 (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.)
010: Port 2 (GLIU0 = Interface to GLIU1; GLIU1 = VP.)
011: Port 3 (GLIU0 = CPU Core; GLIU1 = GLCP.)
100: Port 4 (GLIU0 = DC; GLIU1 = GLPCI.)
101: Port 5 (GLIU0 = GP; GLIU1 = VIP.)
110: Port 6 (GLIU0 = Not Used; GLIU1 = SB.)
111: Port 7 (GLIU0 = Not Used; GLIU1 = Not Used.)
Compare Bizzaro Flag.
0: Consider only transactions whose Bizzaro flag is low as a potentially valid address hit.
1: Consider only transactions whose Bizzaro flag is high as a potentially valid address
Reserved.
Physical Memory Address Base. These bits form the matching value against which the
masked value of the physical address, bits [31:12] are directly compared. If a match is
found, then a “hit’ is declared, depending on the setting of the Bizzaro flag comparator.
Physical Memory Address Mask. These bits are used to mask address bits [31:12] for
the purposes of this ‘hit’ detection.
A low Bizzaro flag indicates a normal transaction cycle such as a memory or I/O.
hit. A high Bizzaro flag indicates a ‘special’ transaction, such as a PCI Shutdown or
Halt cycle.
P2D_BM Bit Descriptions
P2D_BM Register Map
RSVD
GLIU1
MSR Address
Type
Reset Value
PMASK
40000020h-40000029h
P2D_BM[9:0]
R/W
000000FF_FFF00000h
AMD Geode™ LX Processors Data Book
9
8
7
GLIU Register Descriptions
6
5
PBASE
4
3
2
1
0