KC80526LY400128 Intel, KC80526LY400128 Datasheet - Page 10

• Manufacturer Part Number: KC80526LY400128
• Manufacturer: Intel

Specifications of KC80526LY400128

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.1.3.
Table 3 lists the PCI interface signals.
AD[31:0]
C/BE[3:0]#
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
PLOCK#
REQ[4:0]#
GNT[4:0]#
PHOLD#
PHLDA#
PAR
SERR#
CLKRUN#
PCI_RST#
Name
PCI (56 Signals)
CMOS
Type
I/O D
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
I
I
Voltage
V_3
V_3
V_3
V_3
V_3
V_3
V_3
V_3
V_3
V_3
V_3
V_3
V_3
V_3
V_3
V_3
Address/Data: The standard PCI address and data lines. The address is driven with
FRAME# assertion and data is driven or received in following clocks.
Command/Byte Enable: The command is driven with FRAME# assertion and byte
enables corresponding to supplied or requested data is driven on the following clocks.
Frame: Assertion indicates the address phase of a PCI transfer. Negation indicates that
the cycle initiator desires one more data transfer.
Device Select: The 82443DX Host Bridge drives this signal when a PCI initiator is
attempting to access DRAM. DEVSEL# is asserted at medium decode time.
Initiator Ready: Asserted when the initiator is ready for data transfer.
Target Ready: Asserted when the target is ready for data transfer.
Stop: Asserted by the target to request the master to stop the current transaction.
Lock: Indicates an exclusive bus operation and may require multiple transactions to
complete. When LOCK# is asserted, nonexclusive transactions may proceed. The
82443DX supports lock for CPU initiated cycles only. PCI initiated locked cycles are not
supported.
PCI Request: PCI master requests for PCI.
PCI Grant: Permission is given to the master to use PCI.
PCI Hold: This signal comes from the expansion bridge; it is the bridge request for PCI.
The 82443DX Host Bridge will drain the DRAM write buffers, drain the processor-to-PCI
posting buffers, and acquire the host bus before granting the request via PHLDA#. This
ensures that GAT timing is met for ISA masters. The PHOLD# protocol has been
modified to include support for passive release.
PCI Hold Acknowledge: The 82443DX Host Bridge drives this signal to grant PCI to
the expansion bridge. The PHLDA# protocol has been modified to include support for
passive release.
Parity: A single parity bit is provided over AD[31:0] and C/BE[3:0]#.
System Error: The 82443DX asserts this signal to indicate an error condition. Please
refer to the Intel
Clock Run: An open-drain output and input. The 82443DX Host Bridge requests the
central resource (PIIX4E/M) to start or maintain the PCI clock by asserting CLKRUN#.
The 82443DX Host Bridge tri-states CLKRUN# upon deassertion of Reset (since CLK is
running upon deassertion of Reset).
Reset: When asserted, this signal asynchronously resets the 82443DX Host Bridge.
The PCI signals also tri-state, compliant with the PCI Rev 2.1 specifications .
Table 3. PCI Signal Description
440BX PCIset Datasheet for further information.
Intel Celeron
At 400 MHz, 366 MHz, 333 MHz, and 300 MHz
Description
Processor Mobile Module MMC-1
10