KC80526LY400128 Intel, KC80526LY400128 Datasheet - Page 23

• Manufacturer Part Number: KC80526LY400128
• Manufacturer: Intel

Specifications of KC80526LY400128

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

processor to enter the Sleep state. The SLP# signal is not
recognized in the Normal state or the Auto Halt state.
The processor can be reset by the RESET# signal while in
the Sleep state. If RESET# is driven active while the
processor is in the Sleep state, then SLP# and STPCLK#
must immediately be driven inactive to ensure that the
processor correctly initializes itself.
Input signals (other than RESET#) may not change while the
processor is in the Sleep state or transitioning into or out of
the Sleep state. Input signal changes at these times will
cause unpredictable behavior. Thus, the processor is
incapable of snooping or latching any events in the Sleep
state.
While in the Sleep state the processor can enter its lowest
power state, the Deep Sleep state. Removing the
processor’s input clock puts the processor in the Deep Sleep
state. PICCLK may be removed in the Sleep state.
1.
2.
4.5
Table 14 lists the POS and STR typical power specifications.
Normal
Auto Halt
Stop Grant
Quick Start
HALT/Grant
Snoop
Sleep
Deep Sleep
Clock
State
Intel mobile modules do not support shaded clock control states.
Not 100% tested. Specified at 50 C by design/characterization.
1
1
Typical POS and STR Power
N/A
Approximately 10 bus clocks
10 bus clocks
Through snoop, to HALT/Grant Snoop
state: immediate
Through STPCLK#, to Normal state:
10 bus clocks
A few bus clocks after the end of
snoop activity.
To Stop Grant state 10 bus clocks
30 msec
NOTES:
Exit Latency
These are average values of measurement and are guidelines only.
Table 13. Clock State Characteristics
State
POS
STR
Table 14. POS and STR Power
NOTE:
Processor
specified
150 mW
Power
Varies
1.2W
1.2W
0.5W
0.5W
Not
Typical MMC-1 Power
4.4.8
The Deep Sleep state is the lowest power mode the
processor can enter while maintaining its context. Stopping
the BCLK input to the processor enters Sleep state. For
proper operation, the BCLK input should be stopped in the
low state.
The processor will return to the Sleep state or the Quick
Start state from the Deep Sleep state when the BCLK input
is restarted. Due to the PLL lock latency, there is a 30-
millisecond delay after the clocks have started before this
state transition happens. PICCLK may be removed in the
Deep Sleep state. PICCLK should be designed to turn on
when BCLK turns on when transitioning out of the Deep
Sleep state.
The input signal restrictions for the Deep Sleep state are the
same as for the Sleep state, except that RESET# assertion
will result in unpredictable behavior.
Intel Celeron
0.475W
0.018W
Snooping
At 400 MHz, 366 MHz, 333 MHz, and 300 MHz
Yes
Yes
Yes
Yes
Yes
No
No
Deep Sleep State
H/W controlled entry/exit mobile throttling
Normal program execution
S/W controlled entry idle mode
H/W controlled entry/exit mobile throttling
Supports snooping in the low power
states
H/W controlled entry/exit desktop idle
mode support
H/W controlled entry/exit mobile
powered-on suspend support
Processor Mobile Module MMC-1
System Uses
23