KC80526LY400128 Intel, KC80526LY400128 Datasheet - Page 20

• Manufacturer Part Number: KC80526LY400128
• Manufacturer: Intel

Specifications of KC80526LY400128

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

length guidelines, refer to the Mobile Pentium® II processor /
82443BX PCIset Advanced Platform Recommended Design
and Debug Practices. Refer to the Intel
Datasheet for details on memory device support,
organization, size, and addressing.
4.3.3
The PCI interface of the 82443DX Host Bridge is available at
the connector. The 82443DX Host Bridge supports the PCI
Clockrun protocol for PCI bus power management. In this
protocol, PCI devices assert the CLKRUN# open-drain
signal when they require the use of the PCI interface. Refer
to the PCI Mobile Design Guide for complete details on the
PCI Clockrun protocol.
The 82443DX Host Bridge is responsible for arbitrating the
PCI bus. With the MMC-1 connector the 82443DX Host
Bridge can support up to five PCI bus masters. There are
five PCI Request/Grant pairs, REQ[4:0]# and GNT[4:0]#,
available to the manufacturer’s system electronics.
The PCI interface on the connector is 3.3 volts only. All
devices that drive outputs to a 5.0
supported.
The 82443DX Host Bridge system controller is compliant
with the PCI 2.1 specification, which improves the worst
case PCI bus access latency from earlier PCI specifications.
As detailed in the PCI specification, the 82443DX Host
Bridge supports only Mechanism #1 for accessing PCI
configuration space. This implies that signals AD[31:11] are
available for PCI IDSEL signals. However, since the
82443DX Host Bridge is always device #0, AD11 will never
be asserted during PCI configuration cycles as an IDSEL.
The 82443DX reserves AD12 for the AGPbus, which is not
supported by the MMC-1 connector. Thus, AD13 is the first
available address line usable as an IDSEL. AD18 should be
used by the PIIX4E/M.
4.3.4
The Intel MMC-1 family does not support the AGP graphics
port interface. For AGP information, refer to the Intel
PCI Interface
AGP Feature Set
MAB[12]#
MAB[11]#
MAB[10]
MAB[9]#
MAB[7]#
MAB[6]#
Signal
Table 12. Configuration Straps for the 82443DX Host Bridge System Controller
Host Frequency
Select
In order queue depth
Quick Start select
AGP disable
MM Config
Host Bus Buffer Mode
select
Vt
nominal V
Function
440BX PCIset
oh
level are not
No strap 66-MHz default.
No strap maximum queue depth is set, i.e. 8.
Strapped high on the module for Quick Start mode.
Strapped to disable AGP.
Strapped for MMC-1 compatible mode.
Strapped high on the module for mobile PSB buffers.
4.3.2
Several strap options on the memory address bus define the
behavior of the Celeron processor mobile module
MMC-1after reset. Other straps are allowed to override the
default settings. Table 12 shows the various straps and their
implementation.
Celeron
Connector 2 (MMC-2).
4.4
4.4.1
The Celeron processor mobile module’s clock control
architecture is optimal for notebook designs. The clock
control architecture consists of seven different clock states:
Normal, Stop Grant, Auto Halt, Quick Start, HALT/Grant
Snoop, Sleep, and Deep Sleep. The Auto Halt state provides
a low power clock state that can be controlled through the
software execution of the HLT instruction. The Quick Start
state provides a low-power, low-exit latency clock state that
can be used for hardware controlled “idle” computer states.
The Deep Sleep state provides an extremely low-power
state that can be used for Power-on-Suspend states, which
is an alternative to shutting off the processor’s power.
The exit latency of the Deep Sleep state has been reduced
to 30 microseconds. The Stop Grant and Sleep states are
not available on the Celeron processor mobile module as
these states are intended for desktop or server systems. The
Stop Grant and the Quick Start clock states are mutually
exclusive. For example a strapping option on signal A15#
chooses which state is entered when the STPCLK# signal is
asserted. Strapping the A15# signal to ground at Reset
enables the Quick Start state. Otherwise, asserting the
STPCLK# signal puts the mobile Celeron processor into the
Stop Grant state. The Stop Grant state is useful for SMP
platforms and is not supported on the Celeron processor
mobile module MMC-1. The Quick Start state is available on
the module and provides a significantly lower power level.
Figure 3 provides an illustration of the clocking architecture.
Performing state transitions not shown in Figure 3 is neither
recommended nor supported.
Intel Celeron
Module Default Setting
At 400 MHz, 366 MHz, 333 MHz, and 300 MHz
Processor Mobile Module: Mobile Module
Reset Strap Options
Power Management
Clock Control Architecture
Processor Mobile Module MMC-1
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