KC80526LY400128 Intel, KC80526LY400128 Datasheet - Page 22

• Manufacturer Part Number: KC80526LY400128
• Manufacturer: Intel

Specifications of KC80526LY400128

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

4.4.2
This is the normal operating mode. The processor’s core
clock is running and the processor is actively executing
instructions.
4.4.3
This is a low-power mode entered by the processor through
the execution of the HLT instruction. The power level of this
mode is similar to the Stop Grant state. A transition to the
Normal state is made by a halt break event (one of the
following signals going active: NMI, INTR, BINIT#, INIT#,
RESET#, FLUSH#, or SMI#).
Asserting the STPCLK# signal while in the Auto Halt state
will cause the processor to transition to the Stop Grant or
Quick Start state, which issues a Stop Grant Acknowledge
bus cycle. Deasserting STPCLK# will cause the processor to
return to the Auto Halt state without issuing a new Halt bus
cycle.
The SMI# (System Management Interrupt) is recognized in
the Auto Halt state. Returning from the SMI handler can be
to either the Normal state or the Auto Halt state. See the
Intel
III: System Programmer’s Guide for more information. No
Halt bus cycle is issued when returning to the Auto Halt state
from System Management Mode (SMM).
The FLUSH# signal is serviced in the Auto Halt state. After
flushing the on-chip, the processor will return to the Auto
Halt state without issuing a Halt bus cycle. Transitions in the
A20M# and PREQ# signals are recognized while in the Auto
Halt state.
4.4.4
Intel mobile modules do not support the Stop Grant state.
The processor enters this mode with the assertion of the
STPCLK# signal when it is configured for Stop Grant state
(via the A15# strapping option). The processor still responds
to snoop requests and latch interrupts. Latched interrupts will
be serviced when the processor returns to the Normal state.
Only one occurrence of each interrupt event will be latched.
A transition back to the Normal state can be made by the
deassertion of the STPCLK# signal or the occurrence of a
stop break event (a BINIT#, FLUSH#, or RESET# assertion).
The processor will return to the Stop Grant state after the
completion of a BINIT# bus initialization unless STPCLK#
has been deasserted. RESET# assertion will cause the
processor to immediately initialize itself, but the processor
will stay in the Stop Grant state after initialization until
STPCLK# is deasserted. If the FLUSH# signal is asserted,
the processor will flush the on-chip caches and return to the
Stop Grant state. A transition to the Sleep state can be made
by the assertion of the SLP# signal.
While in the Stop Grant state, assertions of SMI#, INIT#,
INTR, and NMI (or LINT[1:0]) will be latched by the
®
Architecture Software Developer’s Manual, Volume
Normal State
Auto Halt State
Stop Grant State
processor. These latched events will not be serviced until the
processor returns to the Normal state. Only one of each
event will be recognized upon return to the Normal state.
4.4.5
This is a mode entered by the processor with the assertion
of the STPCLK# signal when it is configured for the Quick
Start state (via the A15# strapping option). In the Quick Start
state the processor is only capable of acting on snoop
transactions generated by the PSB priority device. Because
of its snooping behavior, Quick Start can only be used in
single processor configurations.
A transition to the Deep Sleep state can be made by
stopping the clock input to the processor. A transition back to
the Normal state (from the Quick Start state) is made only if
the STPCLK# signal is deasserted.
While in this state the processor is limited in its ability to
respond to input. It is incapable of latching any interrupts,
servicing snoop transactions from symmetric bus masters, or
responding to FLUSH# or BINIT# assertions. While the
processor is in the Quick Start state, it will not respond
properly to any input signal other than STPCLK#, RESET#,
or BPRI#. If any other input signal changes, then the
behavior of the processor will be unpredictable. No serial
interrupt messages may begin or be in progress while the
processor is in the Quick Start state.
RESET# assertion will cause the processor to immediately
initialize itself, but the processor will stay in the Quick Start
state after initialization until STPCLK# is deasserted.
4.4.6
The processor will respond to snoop transactions on the
PSB while in the Auto Halt state, the Stop Grant state, or the
Quick Start state. When a snoop transaction is presented on
the PSB the processor will enter the HALT/Grant Snoop
state. The processor will remain in this state until the snoop
has been serviced and the PSB is quiet. After the snoop has
been serviced, the processor will return to its previous state.
If the HALT/Grant Snoop state is entered from the Quick
Start state, then the input signal restrictions of the Quick
Start state still apply in the HALT/Grant Snoop state, except
for those signal transitions that are required to perform the
snoop.
4.4.7
Intel mobile modules do not support the Sleep state.
The Sleep state is a very low power state in which the
processor maintains its context and the phase-locked loop
(PLL) maintains phase lock. The Sleep state can only be
entered from the Stop Grant state. After entering the Stop
Grant state the SLP# signal can be asserted, causing the
Intel Celeron
At 400 MHz, 366 MHz, 333 MHz, and 300 MHz
Quick Start State
HALT/Grant Snoop State
Sleep State
Processor Mobile Module MMC-1
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