KC80526LY400128 Intel, KC80526LY400128 Datasheet - Page 25

• Manufacturer Part Number: KC80526LY400128
• Manufacturer: Intel

Specifications of KC80526LY400128

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

4.6.2
Table 16 provides the PSB clock (BCLK) AC requirements
for the Celeron processor mobile module MMC-1.
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
T#
PSB Frequency
T1:
T2:
T3:
T4:
T5:
T6:
AC Requirements
Unless otherwise noted, all specifications in this table apply to all Intel mobile modules.
All AC timings for the GTL+ signals are referenced to the BCLK rising edge at 1.25V at the processor core pin. All GTL+ signal
timings (address bus, data bus, etc.) are referenced at 1.00V at the processor core pins.
All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25V at the processor core pin. All CMOS signal
timings (compatibility signals, etc.) are referenced at 1.25V at the processor core pins.
The internal core clock frequency is derived from the PSB clock. The PSB clock to core clock ratio is determined during
initialization as described and is predetermined by the Celeron processor mobile module.
The BCLK period allows +0.5 ns tolerance for clock driver variation. See the CK97 Clock Synthesizer/Driver Specification for
further information.
Measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted for as a component of BCLK skew
between devices.
The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the jitter created by the
clock driver. The -20 dB attenuation point, as measured into a 10-pF to 20-pF load, should be less than 500 kHz. This
specification may be ensured by design characterization and/or measured with a spectrum analyzer. See the CK97 Clock
Synthesizer/Driver Specification for further details.
Not 100% tested. Specified by design characterization as a clock driver requirement.
Parameter
BCLK Period
BCLK Period Stability
BCLK High Time
BCLK Low Time
BCLK Rise Time
BCLK Fall Time
4
Table 16. BCLK AC Specifications at the Processor Core Pins
4,5
8
8
6,7,8
0.175
0.175
Min
5.3
5.3
66.67
Nom
15.0
0.875
0.875
Intel Celeron
±250
Max
At 400 MHz, 366 MHz, 333 MHz, and 300 MHz
Unit
MHz
ns
ps
ns
ns
ns
ns
Figure
Processor Mobile Module MMC-1
1,2,3
All processor core
frequencies
At >1.8V
At <0.7V
(0.9V-1.6V)
(1.6V-0.9V)
Notes
25