82V3380PFG IDT, Integrated Device Technology Inc, 82V3380PFG Datasheet - Page 130
82V3380PFG
Manufacturer Part Number
82V3380PFG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82V3380PFG.pdf
(175 pages)
Specifications of 82V3380PFG
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
100
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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PHASE_LOSS_FINE_LIMIT_CNFG - Phase Loss Fine Detector Limit Configuration *
Programming Information
IDT82V3380
Address: 5BH
Type: Read / Write
Default Value: 10XXX010
FINE_PH_LOS_
5 - 3
2 - 0
LIMT_EN
Bit
7
6
7
FINE_PH_LOS_LIMT_EN
PH_LOS_FINE_LIMT[2:0]
FAST_LOS_SW
FAST_LOS_SW
Name
-
6
Reserved.
This bit controls whether the occurrence of the fine phase loss will result in the T0/T4 DPLL unlocked.
0: Disabled.
1: Enabled. (default)
The value in this bit can be switched only when it is available for T0 path; this bit is always ‘1’ when it is available for T4
path.
This bit controls whether the occurrence of the fast loss will result in the T0/T4 DPLL unlocked.
0: Does not result in the T0 DPLL unlocked. T0 DPLL will enter Temp-Holdover mode automatically. (default)
1: Results in the T0/T4 DPLL unlocked. For T0 path, T0 DPLL will enter Lost-Phase mode if the T0 DPLL operating
mode is switched automatically.
These bits set a fine phase limit.
000: 0.
001: ± (45 ° ~ 90 °).
010: ± (90 ° ~ 180 °). (default)
011: ± (180 ° ~ 360 °).
100: ± (20 ns ~ 25 ns).
101: ± (60 ns ~ 65 ns).
110: ± (120 ns ~ 125 ns).
111: ± (950 ns ~ 955 ns).
5
-
4
-
130
3
-
Description
PH_LOS_FINE
_LIMT2
2
SYNCHRONOUS ETHERNET WAN PLL
PH_LOS_FINE
_LIMT1
1
PH_LOS_FINE
May 19, 2009
_LIMT0
0
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