82V3380PFG IDT, Integrated Device Technology Inc, 82V3380PFG Datasheet - Page 54
82V3380PFG
Manufacturer Part Number
82V3380PFG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82V3380PFG.pdf
(175 pages)
Specifications of 82V3380PFG
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
100
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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5.3
Microprocessor Interface
Table 37: Read Timing Characteristics in Intel Mode
IDT82V3380
Note:
* Timing with RDY. If RDY is not used, t
Symbol
t
t
t
t
t
pw1
pw2
su1
su2
t
t
t
t
t
t
t
t
t
t
out
T
d1
d2
d4
d5
d6
h1
h2
h3
TI
in
INTEL MODE
(RD rising edge to RD falling edge, or RD rising edge to WR falling edge)
AD[7:0]
Time between consecutive Read-Read or Read-Write accesses
A[6:0]
RDY
CS
WR
RD
RD rising edge to AD[7:0] high impedance delay time
pw1
Valid address after RD rising edge hold time
CS rising edge to RDY release delay time
Valid RD after RDY rising edge hold time
is 3.5T + 10.
Valid CS after RD rising edge hold time
RD rising edge to RDY low delay time
Valid address to valid CS setup time
One cycle time of the master clock
Valid RD to valid data delay time
Valid CS to valid RDY delay time
Valid CS to valid RD setup time
High-Z
Valid RDY pulse width low
High-Z
Valid RD pulse width low
Delay of output pad
Delay of input pad
t
su1
Parameter
Figure 19. Intel Read Timing Diagram
t
d2
t
su2
t
d1
address
t
54
pw2
t
pw1
data
t
h3
4.5T + 10 *
4.5T + 10
t
t
Min
d4
h1
>T
0
0
0
0
0
t
h2
t
SYNCHRONOUS ETHERNET WAN PLL
d5
12.86
Typ
High-Z
t
13
10
13
13
d6
5
5
High-Z
3.5T + 10
Max
May 19, 2009
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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