82V3380PFG IDT, Integrated Device Technology Inc, 82V3380PFG Datasheet - Page 5

• Manufacturer Part Number: 82V3380PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V3380PFG

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table of Contents
9 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 153
PACKAGE DIMENSIONS.................................................................................................................................................... 172
ORDERING INFORMATION................................................................................................................................................ 175
IDT82V3380
8.2 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 151
8.3 HEATSINK EVALUATION .......................................................................................................................................................................... 151
8.4 TQFP EPAD THERMAL RELEASE PATH ................................................................................................................................................. 152
9.1 ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 153
9.2 RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 153
9.3 I/O SPECIFICATIONS ................................................................................................................................................................................. 154
9.4 JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 161
9.5 OUTPUT WANDER GENERATION ............................................................................................................................................................ 164
9.6 INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 165
9.7 OUTPUT CLOCK TIMING ........................................................................................................................................................................... 166
9.3.1
9.3.2
9.3.3
AMI Input / Output Port ................................................................................................................................................................ 154
9.3.1.1
9.3.1.2
9.3.1.3
CMOS Input / Output Port ............................................................................................................................................................ 156
PECL / LVDS Input / Output Port ................................................................................................................................................ 157
9.3.3.1
9.3.3.2
9.3.3.3
Structure ......................................................................................................................................................................... 154
I/O Level ......................................................................................................................................................................... 154
Over-Voltage Protection ................................................................................................................................................. 156
PECL Input / Output Port ................................................................................................................................................ 157
LVDS Input / Output Port ................................................................................................................................................ 159
Single-Ended Input for Differential Input ........................................................................................................................ 160
5
SYNCHRONOUS ETHERNET WAN PLL
May 19, 2009