82V3380PFG IDT, Integrated Device Technology Inc, 82V3380PFG Datasheet - Page 15
82V3380PFG
Manufacturer Part Number
82V3380PFG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82V3380PFG.pdf
(175 pages)
Specifications of 82V3380PFG
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
100
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Table 1: Pin Description (Continued)
Pin Description
IDT82V3380
OUT6_POS
OUT6_NEG
OUT7_POS
OUT7_NEG
OUT8_POS
OUT8_NEG
INT_REQ
Name
OUT2
OUT3
OUT4
OUT5
OUT9
CS
Pin No.
89
90
93
94
34
35
36
37
28
27
95
70
8
pull-up
I/O
O
O
O
O
O
O
O
O
O
I
PECL/LVDS
PECL/LVDS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Type
AMI
Microprocessor Interface
OUT2: Output Clock 2
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz or 155.52 MHz clock is output on this pin.
OUT3: Output Clock 3
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
5 MHz, 10 MHz, 20 MHz, 25 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz,
51.84 MHz, 77.76 MHz, 125 MHz, 155.52 MHz, 156.25 MHz or 312.5 MHz clock is output on
this pin.
OUT4: Output Clock 4
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz or 155.52 MHz clock is output on this pin.
OUT5: Output Clock 5
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz or 155.52 MHz clock is output on this pin.
OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially output on this pair
of pins.
OUT7_POS / OUT7_NEG: Positive / Negative Output Clock 7
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
5 MHz, 10 MHz, 20 MHz, 25 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz,
51.84 MHz, 77.76 MHz, 125 MHz, 155.52 MHz, 156.25 MHz, 311.04 MHz, 312.5 MHz or
622.08 MHz clock is differentially output on this pair of pins.
OUT8_POS / OUT8_NEG: Positive / Negative Output Clock 8
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is differentially output on this
pair of pins.
OUT9: Output Clock 9
A 1.544 MHz (SONET) / 2.048 MHz (SDH) BITS/SSU clock is output on this pin.
CS: Chip Selection
A transition from high to low must occur on this pin for each read or write operation and this
pin should remain low until the operation is over.
INT_REQ: Interrupt Request
This pin is used as an interrupt request. The output characteristics are determined by the
HZ_EN bit (b1, 0CH) and the INT_POL bit (b0, 0CH).
15
Description
SYNCHRONOUS ETHERNET WAN PLL
4
4
4
4
4
4
, N x T1
, N x T1
, N x T1
, N x T1
, N x T1
, N x T1
1
5
5
5
5
5
5
, N x 13.0 MHz
, N x 13.0 MHz
, N x 13.0 MHz
, N x 13.0 MHz
, N x 13.0 MHz
, N x 13.0 MHz
6
6
6
6
6
6
, N x 3.84 MHz
, N x 3.84 MHz
, N x 3.84 MHz
, N x 3.84 MHz
, N x 3.84 MHz
, N x 3.84 MHz
May 19, 2009
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