82V3380PFG IDT, Integrated Device Technology Inc, 82V3380PFG Datasheet - Page 17

• Manufacturer Part Number: 82V3380PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V3380PFG

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table 1: Pin Description (Continued)
Pin Description
IDT82V3380
ALE / SCLK
VDDD1
VDDD2
VDDD3
VDDD4
VDDD5
VDDD6
VDDD7
Name
TRST
RDY
TMS
TCK
TDO
TDI
Pin No.
73
75
23
21
12
16
13
50
61
85
86
2
7
9
pull-down
pull-down
pull-down
pull-up
pull-up
Power
I/O
O
O
I
I
I
I
I
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Type
-
JTAG (per IEEE 1149.1)
ALE: Address Latch Enable
In Multiplexed mode, the address on AD[7:0] pins is sampled into the device on the falling
edge of ALE.
SCLK: Shift Clock
In Serial mode, a shift clock is input on this pin.
Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated
on the active edge of SCLK. The active edge is determined by the CLKE.
In EPROM, Intel and Motorola modes, this pin should be connected to ground.
RDY: Ready/Data Acknowledge
In Multiplexed and Intel modes, a high level on this pin indicates that a read/write cycle is
completed. A low level on this pin indicates that wait state must be inserted.
In Motorola mode, a low level on this pin indicates that valid information on the data bus is
ready for a read operation or acknowledges the acceptance of the written data during a write
operation.
In EPROM and Serial modes, this pin should be connected to ground.
TRST: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK.
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely
retain their state.
TDI: JTAG Test Data Input
The test data is input on this pin. It is clocked into the device on the rising edge of TCK.
TDO: JTAG Test Data Output
The test data is output on this pin. It is clocked out of the device on the falling edge of TCK.
TDO pin outputs a high impedance signal except during the process of data scanning.
This pin can indicate the interrupt of T0 selected input clock fail, as determined by the
LOS_FLAG_ON_TDO bit (b6, 0BH). Refer to
VDDDn: 3.3 V Digital Power Supply
Each VDDDn should be paralleled with ground through a 0.1 µF capacitor.
Power & Ground
17
Description
SYNCHRONOUS ETHERNET WAN PLL
Chapter 3.8.1 Input Clock Validity
1
May 19, 2009
for details.