SSTU32866EC-S NXP Semiconductors, SSTU32866EC-S Datasheet - Page 11
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SSTU32866EC-S
Manufacturer Part Number
SSTU32866EC-S
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SSTU32866EC-S.pdf
(29 pages)
Specifications of SSTU32866EC-S
Logic Family
SSTU
Logical Function
Registered Buffer
Number Of Elements
1
Number Of Bits
25
Number Of Inputs
25
Number Of Outputs
25
High Level Output Current
-8mA
Low Level Output Current
8mA
Package Type
LFBGA
Propagation Delay Time
3ns
Operating Supply Voltage (typ)
1.8V
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Clock-edge Trigger Type
Posit/Negat-Edge
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
450(Min)MHz
Mounting
Surface Mount
Pin Count
96
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Not Compliant
Philips Semiconductors
8. Limiting values
Table 5:
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1]
[2]
[3]
9. Recommended operating conditions
Table 6:
9397 750 14181
Product data sheet
Symbol
V
V
V
I
I
I
I
T
V
Symbol
V
V
V
V
V
V
V
V
V
V
V
IK
OK
O
CCC
stg
DD
I
O
esd
DD
REF
TT
I
IH(AC)
IL(AC)
IH(DC)
IL(DC)
IH
IL
ICR
Stresses beyond those listed under ‘absolute maximum ratings’ may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under ‘recommended operating
conditions’ is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 2.5 V maximum.
Limiting values
Recommended operating conditions
Parameter
supply voltage
receiver input voltage
driver output voltage
input clamp current
output clamp current
continuous output current
continuous current through
each V
storage temperature
electrostatic discharge
voltage
Parameter
supply voltage
reference voltage
termination voltage
input voltage
AC HIGH-level input voltage
AC LOW-level input voltage
DC HIGH-level input voltage
DC LOW-level input voltage
HIGH-level input voltage
LOW-level input voltage
common mode input voltage
range
DD
or GND pin
Conditions
V
V
0 V < V
Human Body Model (HBM); 1.5 k ;
100 pF
Machine Model (MM); 0 ; 200 pF
I
O
< 0 V or V
< 0 V or V
Conditions
data (Dn),
CSR, and
PAR_IN inputs
data (Dn),
CSR, and
PAR_IN inputs
data (Dn),
CSR, and
PAR_IN inputs
data (Dn),
CSR, and
PAR_IN inputs
RESET, Cn
RESET, Cn
CK, CK
Rev. 02 — 11 November 2004
O
< V
I
DD
O
> V
> V
DD
DD
1.8 V DDR2 configurable registered buffer with parity
[1]
[1]
[2]
Min
1.7
0.49
V
0
V
-
V
-
0.65
-
0.675
REF
REF
REF
[1]
+ 250 mV
+ 125 mV
V
V
40 mV
DD
DD
Typ
-
0.50
V
-
-
-
-
-
-
-
-
REF
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Min
-
-
-
-
2
200
0.5
0.5
0.5
65
V
DD
[2]
[2]
SSTU32866
Max
1.9
0.51
V
V
-
V
-
V
-
0.35
1.125
Max
+2.5
+2.5
V
+150
-
-
REF
DD
REF
REF
50
50
50
100
DD
+ 40 mV
+ 0.5
[3]
V
V
250 mV
125 mV
DD
DD
[3]
Unit
V
V
V
mA
mA
mA
mA
kV
V
11 of 29
C
Unit
V
V
V
V
V
V
V
V
V
V
V