SSTU32866EC-S NXP Semiconductors, SSTU32866EC-S Datasheet - Page 8
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SSTU32866EC-S
Manufacturer Part Number
SSTU32866EC-S
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SSTU32866EC-S.pdf
(29 pages)
Specifications of SSTU32866EC-S
Logic Family
SSTU
Logical Function
Registered Buffer
Number Of Elements
1
Number Of Bits
25
Number Of Inputs
25
Number Of Outputs
25
High Level Output Current
-8mA
Low Level Output Current
8mA
Package Type
LFBGA
Propagation Delay Time
3ns
Operating Supply Voltage (typ)
1.8V
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Clock-edge Trigger Type
Posit/Negat-Edge
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
450(Min)MHz
Mounting
Surface Mount
Pin Count
96
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Not Compliant
Philips Semiconductors
7. Functional description
9397 750 14181
Product data sheet
Table 2:
[1]
[2]
[3]
The SSTU32866 is a 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity,
designed for 1.7 V to 1.9 V V
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control and reset (RESET) inputs are LVCMOS. All data outputs are 1.8 V CMOS drivers
that have been optimized to drive the DDR2 DIMM load, and meet SSTL_18
specifications. The error (QERR) output is 1.8 V open-drain driver.
The SSTU32866 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.
The C0 input controls the pinout configuration for the 1:2 pinout from A configuration
(when LOW) to B configuration (when HIGH). The C1 input controls the pinout
configuration from 25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH).
The SSTU32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN)
input, compares it with the data received on the DIMM-independent D-inputs and
indicates whether a parity error has occurred on its open-drain QERR pin (active-LOW).
The convention is even parity, i.e., valid parity is defined as an even number of ones
across the DIMM-independent data inputs combined with the parity input bit.
When used as a single device, the C0 and C1 inputs are tied LOW. In this configuration,
parity is checked on the PAR_IN input which arrives one cycle after the input data to which
it applies. The partial-parity-out (PPO) and QERR signals are produced three cycles after
the corresponding data inputs.
When used in pairs, the C0 input of the first register is tied LOW and the C0 input of the
second register is tied HIGH. The C1 input of both registers are tied HIGH. Parity, which
arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of
the first device. The PPO and QERR signals are produced on the second device three
clock cycles after the corresponding data inputs. The PPO output of the first register is
Symbol
QERR
n.c.
d.n.u.
Depends on configuration. Refer to
Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0.
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1.
Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.
Pin description
Pin
D2
[1]
[1]
Rev. 02 — 11 November 2004
…continued
DD
operation.
1.8 V DDR2 configurable registered buffer with parity
Figure
Type
open-drain
output
-
-
4,
Figure
5, and
Description
Output error bit. Generated one clock
cycle after the corresponding data output
Not connected. Ball present but no
internal connection to the die.
Do not use. Inputs are in
standby-equivalent mode and outputs
are driven LOW.
Figure 6
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
for ball number.
SSTU32866
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