SSTU32866EC-S NXP Semiconductors, SSTU32866EC-S Datasheet - Page 4
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SSTU32866EC-S
Manufacturer Part Number
SSTU32866EC-S
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SSTU32866EC-S.pdf
(29 pages)
Specifications of SSTU32866EC-S
Logic Family
SSTU
Logical Function
Registered Buffer
Number Of Elements
1
Number Of Bits
25
Number Of Inputs
25
Number Of Outputs
25
High Level Output Current
-8mA
Low Level Output Current
8mA
Package Type
LFBGA
Propagation Delay Time
3ns
Operating Supply Voltage (typ)
1.8V
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Clock-edge Trigger Type
Posit/Negat-Edge
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
450(Min)MHz
Mounting
Surface Mount
Pin Count
96
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Not Compliant
Philips Semiconductors
9397 750 14181
Product data sheet
Fig 2. Parity logic diagram for 1:2 Register A configuration (positive logic); C0 = 0, C1 = 1
D2, D3, D5, D6,
D8 to D14
PAR_IN
RESET
V
REF
CK
CK
C1
C0
11
D2, D3, D5, D6,
R
COUNTER
(internal node)
CLK
2-BIT
D8 to D14
D
R
D
R
LPS0
CLK
CLK
CE
Rev. 02 — 11 November 2004
PARITY
CHECK
11
0
1
1.8 V DDR2 configurable registered buffer with parity
(internal node)
LPS1
D
R
CLK
CE
11
D2, D3, D5, D6,
D8 to D14
D
R
CLK
D
R
CLK
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
0
1
1
0
002aaa650
SSTU32866
11
11
Q2A, Q3A,
Q5A, Q6A,
Q8A to Q14A
Q2B, Q3B,
Q5B, Q6B,
Q8B to Q14B
PPO
QERR
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