LMK04031BISQ National Semiconductor, LMK04031BISQ Datasheet - Page 27

• Manufacturer Part Number: LMK04031BISQ
• Manufacturer: National Semiconductor

Specifications of LMK04031BISQ

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

The Lock Detect (LD) signal can be connected to the GOE
pin in which case all outputs are disabled automatically if the
synthesizer is not locked. See
Clock Channel Output Enable
TEM LEVEL DIAGRAM
The Lock Detect (LD) pin can be programmed to output a
‘High’ when both PLL1 and PLL2 are locked, or only when
PLL1 is locked or only when PLL2 is locked.
15.0 Functional Description
15.1 ARCHITECTURAL OVERVIEW
The LMK040xx chip consists of two high performance syn-
thesizer blocks (Phase Locked Loop, internal VCO/VCO Di-
vider, and loop filter), source selection, distribution system,
and independent clock output channels.
The Phase Frequency Detector in PLL1 compares the divided
(R Divider 1) system clock signal from the selected CLKinX
and CLKinX* input with the divided (N Divider 1) output of the
external VCXO attached to the PLL2 OSCin port. The external
loop filter for PLL1 should be narrow to provide an ultra clean
reference clock from the external VCXO to the OSCin/OSCin*
pins for PLL2.
The Phase Frequency Detector in PLL2 then compares the
divided (R Divider 2) reference signal from the PLL2 OSCin
port with the divided (N Divider 2 and VCO Divider) output of
the internal VCO. The bandwidth of the external loop filter for
PLL2 should be designed to be wide enough to take advan-
tage of the low in-band phase noise of PLL2 and the low high
offset phase noise of the internal VCO. The VCO output is
passed through a common VCO divider block and placed on
a distribution path for the clock distribution section. It is also
routed to the PLL2_N counter. Each clock output channel al-
lows the user to select a path with a programmable divider
block, a phase synchronization circuit, a programmable de-
lay, and LVDS/LVPECL/2VPECL/LVCMOS compatible out-
put buffers.
15.2 PHASE DETECTOR 1 (PD1)
Phase Detector 1 in PLL1 (PD1) can operate up to 40 MHz.
Since a narrow loop bandwidth should be used for PLL1, the
need to operate at high phase detector rate to lower the in-
band phase noise becomes unnecessary.
15.3 PHASE DETECTOR 2 (PD2)
Phase Detector 2 in PLL2 (PD2) supports a maximum com-
parison rate of 100 MHz, though the actual maximum fre-
quency at the input port (PLL2 OSCin/OSCin*) is 250 MHz.
Operating at highest possible phase detector rate will ensure
low in-band phase noise for PLL2 which in turn produces low-
er total jitter, as the in-band phase noise from the reference
input and PLL are proportional to N
15.4 PLL2 FREQUENCY DOUBLER
The PLL2 reference input at the OSCin port may be optionally
routed through a frequency doubler function rather than
for actual implementation details.
Section 16.3.2 EN_CLKoutX:
and also
2
.
Section 17.1 SYS-
27
through the PLL2_R counter. The maximum phase compari-
son frequency of the PLL2 phase detector is 100 MHz, so the
input to the frequency doubler is limited to a maximum of 50
MHz. The frequency doubler feature allows the phase com-
parison frequency to be increased when a relative low fre-
quency oscillator is driving the OSCin port. By doubling the
PLL2 phase comparison frequency, the in-band PLL2 noise
is reduced by about 3 dB.
15.5 INPUTS / OUTPUTS
15.5.1 PLL1 Reference Inputs (CLKin0 / CLKin0*, CLKin1 /
CLKin1*)
The reference clock inputs for PLL1 may be selected from
either CLKin0 and CLKin1. The user has the capability to
manually select one of the two inputs or to configure an au-
tomatic switching mode operation. A detailed description of
this function is described in the uWire programming section
of this data sheet.
15.5.2 PLL2 OSCin / OSCin* Port
The feedback from the external oscillator being locked with
PLL1 is injected to the PLL2 OSCin/OSCin* pins. This input
may be driven with either a single- ended or differential signal.
If operated in single ended mode, the unused input should be
tied to GND with a 0.1 µF capacitor. Either AC or DC coupling
is acceptable. Internal to the chip, this signal is routed to the
PLL1_N Counter and to the reference input for PLL2. The in-
ternal circuitry of the OSCin port also supports the optional
implementation of a crystal based oscillator circuit. A crystal,
varactor diode and a small number of other external compo-
nents may be used to implement the oscillator. The internal
oscillator circuit is enabled by setting the EN_PLL2_XTAL bit.
15.5.3 CPout1 / CPout2
The CPout1 pin provides the charge pump current output to
drive the loop filter for PLL1. This loop filter should be config-
ured so that the total loop bandwidth for PLL1 is less than 200
Hz. When combined with an external oscillator that has low
phase noise at offsets close to the carrier, PLL1 generates a
reference for PLL2 that is frequency locked to the PLL1 ref-
erence clock but has the phase noise performance of the
oscillator. The CPout2 pin provides the charge pump current
output to drive the loop filter for PLL2. This loop filter should
be configured so that the total loop bandwidth for PLL2 is in
the range of 50 kHz to 200 kHz. See the section on uWire
device control for a description of the charge pump current
gain control.
15.5.4 Fout
The buffered output of the internal VCO is available at the
Fout pin. This is a single-ended output (sinusoid). Each time
the PLL2_N counter value is updated via the uWire interface,
an internal algorithm is triggered that optimizes the VCO per-
formance.
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