LMK04031BISQ National Semiconductor, LMK04031BISQ Datasheet - Page 49

• Manufacturer Part Number: LMK04031BISQ
• Manufacturer: National Semiconductor

Specifications of LMK04031BISQ

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

17.9 DRIVING CLKin AND OSCin INPUTS
17.9.1 Driving CLKin Pins with a Differential Source
Both CLKin ports can be driven by differential signals. It is
recommended that the input mode be set to bipolar
(CLKinX_TYPE = 0) when using differential reference clocks.
The LMK04000 family internally biases the input pins so the
differential interface should be AC coupled. The recommend-
ed circuits for driving the CLKin pins with either LVDS or
LVPECL are shown in
Finally, a reference clock source that produces a differential
sinewave output can drive the CLKin pins using the following
circuit. Note: the signal level must conform to the require-
ments for the CLKin pins listed in the Electrical Characteristics
table.
17.9.2 Driving CLKin Pins with a Single-Ended Source
The CLKin pins of the LMK04000 family can be driven using
a single-ended reference clock source, for example, either a
sinewave source or an LVCMOS/LVTTL source. Either AC
coupling or DC coupling may be used. In the case of the
sinewave source that is expecting a 50 Ω load, it is recom-
mended that AC coupling be used as shown in the circuit
below with a 50 Ω termination..
Note: The signal level must conform to the requirements for the CLKin pins
FIGURE 19. CLKinX/X* Termination for a Differential
FIGURE 18. CLKinX/X* Termination for an LVPECL
FIGURE 17. CLKinX/X* Termination for an LVDS
listed in the Electrical Characteristics table. CLKinX_TYPE in Regis-
ter 11 is recommended to be set to bipolar mode (CLKinX_TYPE =
0).
Sinewave Reference Clock Source
Reference Clock Source
Reference Clock Source
Figure 17
and
Figure
18.
30027124
30027181
30027187
49
If the CLKin pins are being driven with a single-ended LVC-
MOS/LVTTL source, either DC coupling or AC coupling may
be used. If DC coupling is used, the CLKinX_TYPE should be
set to MOS buffer mode (CLKinX_TYPE = 1) and the voltage
swing of the source must meet the specifications for DC cou-
pled, MOS-mode clock inputs given in the table of Electrical
Characteristics. If AC coupling is used, the CLKinX_TYPE
should be set to the bipolar buffer mode (CLKinX_TYPE = 0).
The voltage swing at the input pins must meet the specifica-
tions for AC coupled, bipolar mode clock inputs given in the
table of Electrical Characteristics. In this case, some attenu-
ation of the clock input level may be required. A simple
resistive divider circuit before the AC coupling capacitor is
sufficient.
17.10 ADDITIONAL OUTPUTS WITH AN LMK04000
FAMILY DEVICE
The number of outputs on a LMK04000 family device can be
expanded in many ways. The first method is to use the dif-
ferential outputs as two single-ended outputs. For CMOS
outputs, both the positive and negative outputs can be pro-
grammed to be in phase, or 180 degrees out of phase. LVDS/
LVPECL positive and negative outputs are always 180 de-
grees out of phase. LVDS single-ended is not recommended.
In addition to this technique, the number of outputs can be
expanded with a LMK01000 family device. To do this, one of
the clock outputs of a LMK04000 can drive the LMK01000
device. For more information on phase synchronication with
multiple devices, please refer to application note AN-1864:
http://www.national.com/an/AN/AN-1864.pdf.
17.11 OUTPUT CLOCK PHASE NOISE PERFORMANCE
VS. VCXO PHASE NOISE
The jitter cleaning capability of the LMK04000 family is highly
dependent on the phase noise performance of the VCXO (or
crystal) that is integrated with PLL1. The VCXO is the refer-
ence for PLL2 which provides the clock for the output distri-
bution path. Consequently, the designer must choose a
VCXO (or crystal) that supports the required performance at
the clock outputs.
An example of the difference in performance that can be ob-
tained from various VCXOs is illustrated in the following plots.
FIGURE 21. DC Coupled LVCMOS/LVTTL Reference
FIGURE 20. CLKinX/X* Single-ended Termination
Clock
www.national.com
30027185
30027122