LMK04031BISQ National Semiconductor, LMK04031BISQ Datasheet - Page 43

• Manufacturer Part Number: LMK04031BISQ
• Manufacturer: National Semiconductor

Specifications of LMK04031BISQ

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

17.4 CURRENT CONSUMPTION / POWER DISSIPATION
CALCULATIONS
Due to the myriad of possible configurations the following ta-
ble serves to provide enough information to allow the user to
calculate estimated current consumption of the device. Un-
less otherwise noted V
From
any configuration. For example, the current for the entire de-
vice with 1 LVDS (CLKout0) & 1 LVPECL (CLKout1) output
in bypassed mode can be calculated by adding up the follow-
ing blocks: core current, clock buffer, one LVDS output buffer
current, and one LVPECL output buffer current. There will al-
so be one LVPECL output drawing emitter current, but some
of the power from the current draw is dissipated in the external
120 Ω resistors which doesn't add to the power dissipation
budget for the device. If delays or divides are switched in, then
the additional current for these stages needs to be added as
well.
For power dissipated by the device, the total current entering
the device is multiplied by the voltage at the device minus the
power dissipated in any emitter resistors connected to any of
the LVPECL outputs. If no emitter resistors are connected to
the LVPECL outputs, this power will be 0 watts. For example,
in the case of 1 LVDS (CLKout0) & 1 LVPECL (CLKout1) op-
erating at 3.3 V, we calculate 3.3 V × (115 + 10 + 10 + 19.3 +
40) mA = 3.3 V × 194.3 mA = 641.2 mW. Because the
LVPECL output (CLKout1) has the emitter resistors hooked
up and the power dissipated by these resistors is 50 mW, the
total device power dissipation is 641.2 mW - 50 mW = 591.2
mW.
When the LVPECL output is active, ~1.7 V is the average
voltage on each output as calculated from the LVPECL V
& V
each emitter resistor is approximately (1.7 V)
mW. When the LVPECL output is disabled, the emitter resis-
tor voltage is ~1.07 V. Therefore the power dissipated in each
emitter resistor is approximately (1.07 V)
17.5 POWER SUPPLY CONDITIONING
The recommended technique for power supply management
is to connect the power pins for the clock outputs (pins 13, 37,
40, 43, and 46) to a dedicated power plane and connect all
other power pins on the device (pins 3, 8, 18, 19, 22, 24, 30,
31, and 33) to a second power plane. Note: the LMK04000
family has internal voltage regulators for the PLL and VCO
blocks to provide noise immunity.
17.6 THERMAL MANAGEMENT
Power consumption of the LMK04000 family of devices can
be high enough to require attention to thermal management.
OL
Table 31
typical specification. Therefore the power dissipated in
the current consumption can be calculated in
CC
= 3.3 V, T
A
= 25 °C.
2
/ 120 Ω = 9.5 mW.
2
/ 120 Ω = 25
OH
43
For reliability and performance reasons the die temperature
should be limited to a maximum of 125 °C. That is, as an es-
timate, T
sumption times θ
The package of the device has an exposed pad that provides
the primary heat removal path as well as excellent electrical
grounding to a printed circuit board. To maximize the removal
of heat from the package a thermal land pattern including
multiple vias to a ground plane must be incorporated on the
PCB within the footprint of the package. The exposed pad
must be soldered down to ensure adequate heat conduction
out of the package. A recommended land and via pattern is
shown in
ages can be obtained: http:// www.national.com/analog/pack-
aging/.
To minimize junction temperature it is recommended that a
simple heat sink be built into the PCB (if the ground plane
layer is not exposed). This is done by including a copper area
of about 2 square inches on the opposite side of the PCB from
the device. This copper area may be plated or solder coated
to prevent corrosion but should not have conformal coating (if
possible), which could provide thermal insulation. The vias
shown in
per layers and to the ground layer. These vias act as “heat
pipes” to carry the thermal energy away from the device side
of the board to where it can be more effectively dissipated.
FIGURE 5. Recommended Land and Via Pattern
A
Figure 5
Figure
(ambient temperature) plus device power con-
5. More information on soldering LLP pack-
JA
should connect these top and bottom cop-
should not exceed 125 °C.
www.national.com
30027173