LMK04031BISQ National Semiconductor, LMK04031BISQ Datasheet - Page 36

• Manufacturer Part Number: LMK04031BISQ
• Manufacturer: National Semiconductor

Specifications of LMK04031BISQ

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

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16.9.2 PLL1_R: PLL1_R Counter
The size of the PLL1_R counter is 12 bits. This counter will
support a maximum divide ratio of 4095 and minimum divide
ratio of 1.
16.9.3 PLL1 Charge Pump Current Gain (PLL1_CP_GAIN)
and Polarity Control (PLL1_CP_POL)
The Loop Band Width (LBW) on PLL1 should be narrow to
suppress the noise from the system or input clocks at CLKinX/
CLKinX* port. This configuration allows the noise of the ex-
ternal VCXO to dominate at low offset frequencies. Given that
the noise of the external VCXO is far superior than the noise
of PLL1, this setting produces a very clean reference clock to
PLL2 at the OSCin port.
In order to achieve a LBW as low as 10 Hz at the supported
VCXO frequency (1 MHz to 200 MHz), a range of charge
pump currents in PLL1 is provided. The table below shows
the available current gains. A small charge pump current is
required to obtain a narrow LBW at high phase detector rate
(small N value).
The PLL1_CP_POL bit sets the PLL1 charge pump for oper-
ation with a positive or negative slope VCO/VCXO. A positive
slope VCO/VCXO increases frequency with increased tuning
voltage. A negative slope VCO/VCXO increases frequency
with decreased tuning voltage.
16.10 REGISTER 13
16.10.1 EN_PLL2_XTAL: Crystal Oscillator Option Enable
If an external crystal is being used to implement a discrete
VCXO, the internal feedback amplifier must be enabled in or-
der to complete the oscillator circuit.
PLL1_CP_POL
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
0
0
1
.
b2
TABLE 17. PLL1 Charge Pump Polarity Control Bits
PLL1_CP_GAIN
0
0
0
0
1
1
1
1
TABLE 16. PLL1 Charge Pump Current Selections
0
0
1
.
0
1
[2:0]
b1
0
0
1
1
0
0
1
1
TABLE 15. PLL1_R Counter Values
0
0
1
.
0
0
1
.
b0
0
1
0
1
0
1
0
1
0
0
1
.
(PLL1_CP_GAIN)
R [11:0]
(PLL1_CP_POL)
0
0
1
.
Negative Slope VCO/VCXO
Positive Slope VCO/VCXO
PLL1 Charge Pump Current
0
0
1
.
DESCRIPTION
0
0
1
.
Magnitude (µA)
RESERVED
RESERVED
0
0
1
.
100
400
20
80
25
50
0
0
1
.
0
0
1
.
0
1
1
.
VALUE
Valid
4095
Not
...
1
36
16.10.2 EN_Fout: Fout Power Down Bit
The EN_Fout bit allows the Fout port to be enabled or dis-
abled. By default EN_Fout = 0.
16.10.3 CLK Global Enable: Clock Global enable bit
In addition to the external GOE pin, an internal Register 13 bit
(b18) can be used to globally enable/disable the clock outputs
via the uWire programming interface. The default value is 1.
When CLK Global Enable = 1, the active output clocks are
enabled. The active output clocks are disabled if this bit is 0.
16.10.4 POWERDOWN Bit -- Device Power Down
This bit can power down the entire device. Enabling this bit
powers down the entire device and all functional blocks, re-
gardless of the state of any of the other bits or pins.
16.10.5 EN_PLL2 REF2X: PLL2 Frequency Doubler
control bit
When F
can be enabled by setting EN_PLL2_REF2X = 1. The default
value is 0. When EN_PLL2_REF2X = 1, the signal at the OS-
Cin port bypasses the PLL2_R counter and is passed through
a frequency doubler circuit. The output of this circuit is then
input to the PLL2 phase comparator block. This feature allows
the phase comparison frequency to be increased for lower
frequency OSCin sources (< 50 MHz), and can be used with
either VXCOs or crystals. For instance, when using a pullable
crystal of 12.288 MHz to drive the OSCin port, the PLL2 phase
comparison frequency is 24.576 MHz when EN_PLL2_RE-
F2X = 1. A higher PLL phase comparison frequency reduces
PLL2 in-band phase noise and RMS jitter. The PLL in-band
phase noise can be reduced by approximately 2 to 3 dB. The
on-chip loop filter typically is enabled to reduce PLL2 refer-
ence spurs when EN_PLL2_REF2X is enabled. Suggested
values in this case are: R3 = 600 Ω, C3 = 50 pF, R4 = 10
kΩ, C4 = 60 pF.
16.10.6 PLL2 Internal Loop Filter Component Values
Internal loop filter components are available for PLL2, en-
abling the user to implement either 3rd or 4th order loop filters
without requiring external components. The user may select
from a fixed set of values for both the resistors and capacitors.
Internal loop filter resistance values for R3 and R4 can be set
individually according to Table 20 and Table 21.
POWERDOWN
TABLE 18. EN_PLL2_XTAL: External Crystal Option
EN_PLL2_XTAL
OSCin
Bit
0
1
TABLE 19. Power Down Bit Values
is below 50 MHz, the PLL2 frequency doubler
0
1
Entire device powered down
Normal Operation
Oscillator Amplifier State
Mode
OFF
ON