LMK04031BISQ National Semiconductor, LMK04031BISQ Datasheet - Page 35

• Manufacturer Part Number: LMK04031BISQ
• Manufacturer: National Semiconductor

Specifications of LMK04031BISQ

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

16.8.2 CLKin_SEL: PLL1 Reference Clock Selection and
Revertive Mode Control Bits
This register allows the user to set the reference clock input
that is used to lock PLL1, or to select an auto-switching mode.
The automatic switching modes are revertive or non-re-
vertive. In either revertive or non-revertive mode, CLKin0 is
the initial default reference source for the auto-switching
mode. When revertive mode is active, the switching control
logic will always select CLKin0 as the reference if it is active,
otherwise it selects CLKin1. When non-revertive mode is ac-
tive, the switching logic will only switch the reference input if
the currently selected input fails.
Table 11
are the auto-switching modes. The behavior of both modes is
tied to the state of the LOS signals for the respective reference
clock inputs.
If the reference clock inputs are active prior to configuration
of the device, then the normal programming sequence de-
scribed under
tion
guaranteed that the reference clocks are active prior to device
programming, then the device programming sequence should
be modified in order to ensure that CLKin0 is selected as the
default. Under this scenario, the device should be pro-
grammed as described in "General Programming Informa-
tion", with CLKin_SEL bits programmed to [0,0] in register
R11. The other R11 fields for clock type and LOS timeout
should be programmed with the appropriate values for the
given application. After the reference clock inputs have start-
ed, register R11 should be programmed a second time with
the CLKin_SEL field modified to the set the desired mode.
The clock type field and LOS field values should remain the
same.
16.8.3 CLKinX_LOS
The CLKin0_LOS and CLKin1_LOS pins indicate the state of
the respective PLL1 CLKinX reference input when the
CLKin_SEL bits are set set to either [1,0] or [1,1]. The detec-
tion logic that determines the state of the reference inputs is
sensitive to the frequency of the reference inputs and must
be configured to operate with the appropriate frequency range
of the reference inputs, as described in the next section.
TABLE 11. CLKin_SEL: Reference Clock Selection Bits
CLKin_SEL [1:0]
b1
0
0
1
1
can be used without modification. If it cannot be
illustrates the control modes. Modes [1,0] and [1,1]
b0
0
1
0
1
Section 16.0 General Programming Informa-
is the default reference clock. If CLKin0
fails, CLKin1 is automatically selected if
remains as the selected reference clock
Non-revertive. Auto-switching. CLKin0
Revertive. Auto-switching. CLKin0 is
the preferred reference clock and is
active. If CLKin0 restarts, CLKin1
Force CLKin0 / CLKin0* as PLL1
Force CLKin1 / CLKin1* as PLL1
unless it fails, then CLKin0 is re-
selected when active.
Function
reference
reference
selected.
35
16.8.4 PLL1 Reference Clock LOS Timeout Control
This register is used to tune the LOS timeout based upon the
frequency of the reference clock input(s). The register value
controls the timeout setting for both CLKin0 and CLKin1. The
value programmed in the LOS_TIMEOUT register represents
the minimum input frequency for which loss of signal can be
detected. For example, if the reference input frequency is
12.288 MHz, then either register values (0,0) or (0,1) will re-
sult in valid loss of signal detection. If the reference input
frequency is 1 MHz, then only the register value (0,0) will re-
sult in valid detection of signal loss.
16.8.5 LOS Output Type Control
The output format of the LOS pins may be selected as active
CMOS, open drain NMOS and open drain PMOS, as shown
in the following table.
TABLE 13. Loss of Signal (LOS) Output Pin Format Type
The LOS output signal is valid only when CLKin_SEL bits are
set to either [1,0] or [1,1]. If the CLKin_SEL field is pro-
grammed to either of the fixed inputs, [0,0] or [0,1], the
LOS_TYPE bits should be set to [0,0].
16.9 REGISTER 12
16.9.1 PLL1_N: PLL1_N Counter
The size of the PLL1_N counter is 12 bits. This counter will
support a maximum divide ratio of 4095 and minimum divide
ratio of 1. The 12 bit resolution is sufficient to support mini-
mum phase detector frequency resolution of approximately
50 kHz when the VCXO frequency is 200 MHz.
For a 200 MHz external VCXO, the minimum phase detector
rate will be PDmin = 200 MHz/4095 = 48.84 kHz
b11 b10 ...
TABLE 12. Reference Clock LOS Timeout Control Bits
0
0
0
1
b1
0
0
1
1
b1
LOS_TYPE [1:0]
0
0
1
1
0
0
0
1
TABLE 14. PLL1_N Counter Values
b0
0
1
0
1
b6 b5 b4 b3 b2 b1 b0
0
0
0
1
.
N [17:0]
b0
0
1
0
1
0
0
0
.
Corresponding Minimum Input
0
0
0
.
0
0
0
.
Functional Description
Frequency
3.0 MHz
13 MHz
32 MHz
NMOS open drain
PMOS open drain
1 MHz
0
0
0
.
Active CMOS
Reserved
0
0
1
.
0
1
0
.
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Not Valid
VALUE
4095
...
1
2