MAX1196ECM+D Maxim Integrated Products, MAX1196ECM+D Datasheet - Page 15

IC ADC 8BIT 40MSPS DL 48-TQFP

MAX1196ECM+D

Manufacturer Part Number
MAX1196ECM+D
Description
IC ADC 8BIT 40MSPS DL 48-TQFP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX1196ECM+D

Number Of Bits
8
Sampling Rate (per Second)
40M
Data Interface
Parallel
Number Of Converters
2
Power Dissipation (max)
108mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
All digital outputs, D0A/B–D7A/B (CHA or CHB data) and
A/B are TTL/CMOS-logic compatible. The output coding
can be chosen to be either offset binary or two’s comple-
ment (Table 1) controlled by a single pin (T/B). Pull T/B
low to select offset binary and high to activate two’s com-
plement output coding. The capacitive load on the digital
outputs D0A/B–D7A/B should be kept as low as possible
(<15pF), to avoid large digital currents that could feed
back into the analog portion of the MAX1196, thereby
degrading its dynamic performance. Using buffers on
the digital outputs of the ADCs can further isolate the
digital outputs from heavy capacitive loads. To further
improve the dynamic performance of the MAX1196,
small-series resistors (e.g., 100Ω) can be added to the
digital output paths, close to the MAX1196.
Figure 4 displays the timing relationship between out-
put enable and data output valid as well as power-
down/wake-up and data output valid.
Figure 4. Output Timing Diagram
Table 1. MAX1196 Output Codes for Differential Inputs
*V
D0A/B–D7A/B
Internal Reference and Multiplexed Parallel Outputs
REF
Digital Output Data, Output Data Format
OUTPUT
DIFFERENTIAL INPUT
= V
OE
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
-V
-V
V
REFP
Selection (T/B), Output Enable (
-V
V
REF
REF
VOLTAGE*
REF
REF
REF
× 255/256
- V
× 255/256
× 256/256
× 1/256
0
× 1/256
HIGH-Z
REFN
______________________________________________________________________________________
t
ENABLE
Channel Selection (A/B)
VALID DATA
t
DIFFERENTIAL INPUT
DISABLE
+Full Scale - 1LSB
-Full Scale + 1LSB
Bipolar Zero
-Full Scale
+1LSB
-1LSB
HIGH-Z
OE ),
The MAX1196 offers two power-save modes—sleep
and full power-down mode. In sleep mode (SLEEP = 1),
only the reference bias circuit is active (both ADCs are
disabled), and current consumption is reduced to 3mA.
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to the power down. Pulling OE high forces
the digital outputs into a high-impedance state.
Figure 5 depicts a typical application circuit containing
two single-ended-to-differential converters. The internal
reference provides a V
ing purposes. The input is buffered and then split to a
voltage follower and inverter. One lowpass filter per
amplifier suppresses some of the wideband noise asso-
ciated with high-speed operational amplifiers. The user
can select the R
performance, to suit a particular application. For the
application in Figure 5, an R
the capacitive load to prevent ringing and oscillation.
The 22pF C
An RF transformer (Figure 6) provides an excellent solu-
tion to convert a single-ended source signal to a fully dif-
ferential signal, required by the MAX1196 for optimum
performance. Connecting the center tap of the trans-
former to COM provides a V
input. Although a 1:1 transformer is shown, a step-up
transformer can be selected to reduce the drive require-
ments. A reduced signal swing from the input driver, such
as an op amp, can also improve the overall distortion.
STRAIGHT OFFSET
1000 0001
1000 0000
0111 1111
0000 0001
1111 1111
0000 0000
BINARY
T/B = 0
IN
capacitor acts as a small filter capacitor.
Applications Information
ISO
Using Transformer Coupling
Power-Down (PD) and Sleep
and C
DD
/2 output voltage for level-shift-
IN
ISO
values to optimize the filter
DD
TWO’S COMPLEMENT
of 50Ω is placed before
/2 DC level shift to the
(SLEEP) Modes
0111 1111
0000 0001
1000 0001
1000 0000
0000 0000
1111 1111
T/B = 1
15

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