MAX1196ECM+D Maxim Integrated Products, MAX1196ECM+D Datasheet - Page 6

• Manufacturer Part Number: MAX1196ECM+D
• Description: IC ADC 8BIT 40MSPS DL 48-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1196ECM+D

• Number Of Bits: 8
• Sampling Rate (per Second): 40M
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 108mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
resistor, V
unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values
are at T
6
Note 1: Guaranteed by design. Not subject to production testing.
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the total input power.
Note 3: Analog attenuation is defined as the amount of attenuation of the fundamental bin from a converted FFT between two
Note 4: REFIN and REFOUT should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor.
Note 5: REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor.
Note 6: Typical digital output current at f
Note 7: See Figure 3 for detailed system timing diagrams. Clock to data valid timing is measured from 50% of the clock level to
Note 8: SINAD settles to within 0.5dB of its typical value in unbuffered external reference mode.
Note 9: Crosstalk rejection is tested by applying a test tone to one channel and holding the other channel at DC level. Crosstalk is
Note 10:Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-
Note 11:Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of
CLK Pulse Width Low
Wake-Up Time
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
DD
_______________________________________________________________________________________
= OV
A
applied input signals with the same magnitude (peak-to-peak) at f
Operating Characteristics.
50% of the data output level.
measured by calculating the power ratio of the fundamental of each channel’s FFT.
mental of the calculated FFT.
the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
= +25°C.)
IN
PARAMETER
DD
= 2V
= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
P-P
(differential with respect to COM), C
SYMBOL
t
WAKE
t
CL
INA&B
= 20MHz. For digital output currents vs. analog input frequency, see the Typical
Clock period: 25ns (Note 7)
Wake-up from sleep mode
Wake-up from shutdown mode (Note 8)
f
f
f
INA or B
INA or B
INA or B
= 20MHz at -1dB FS (Note 9)
= 20MHz at -1dB FS (Note 10)
= 20MHz at -1dB FS (Note 11)
L
= 10pF at digital outputs (Note 5), f
CONDITIONS
IN1
and f
IN2
.
MIN
CLK
= 40MHz, T
±0.05
TYP
12.5
±1.5
0.05
-72
20
1
A
MAX
= T
MIN
D eg r ees
to T
UNITS
dB
dB
ns
µs
MAX
,