MAX1196ECM+D Maxim Integrated Products, MAX1196ECM+D Datasheet - Page 21

• Manufacturer Part Number: MAX1196ECM+D
• Description: IC ADC 8BIT 40MSPS DL 48-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1196ECM+D

• Number Of Bits: 8
• Sampling Rate (per Second): 40M
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 108mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components minus the fundamental
and the DC offset.
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed from:
Figure 11. T/H Aperture Timing
Internal Reference and Multiplexed Parallel Outputs
DATA (T/H)
SAMPLED
Signal-to-Noise Plus Distortion (SINAD)
ANALOG
INPUT
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
CLK
T/H
ENOB
SNR
t
AD
Effective Number of Bits (ENOB)
TRACK
dB[max]
=
______________________________________________________________________________________



Signal-to-Noise Ratio (SNR)
SINAD
= 6.02
t
6.02
HOLD
AJ
- 1.76
dB
× N + 1.76



TRACK
dB
THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:
where V
V
harmonics.
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest spurious
component, excluding DC offset.
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst third-order (or higher)
intermodulation products. The individual input tone lev-
els are at -7dB full scale.
TRANSISTOR COUNT: 11,601
PROCESS: CMOS
5
THD
(Sampling Speed and Resolution)
8-BIT PART
are the amplitudes of the 2nd- through 5th-order
MAX1195
MAX1197
MAX1198
MAX1196
N/A
N/A
Spurious-Free Dynamic Range (SFDR)
=
1
is the fundamental amplitude, and V
20
×
Intermodulation Distortion (IMD)
Total Harmonic Distortion (THD)
Pin-Compatible Upgrades
log




10-BIT PART
MAX1185
MAX1183
MAX1182
MAX1180
MAX1190
MAX1186
V
2
2
+
Chip Information
V
3
2
V
+
1
V
4
SAMPLING SPEED
2
40, multiplexed
+
(Msps)
V
100
120
5
20
40
60
2
2
through




21