LTC1418IG Linear Technology, LTC1418IG Datasheet - Page 22

• Manufacturer Part Number: LTC1418IG
• Description: IC A/D CONV 14BIT SRL&PAR 28SSOP
• Manufacturer: Linear Technology

Specifications of LTC1418IG

• Number Of Bits: 14
• Sampling Rate (per Second): 200k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 21.5mW Unipolar; 31.5mW Bipolar
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS
two zeros. The MSB (D13) will be valid on the first rising
and the first falling edge of the SCLK. D12 will be valid on
the second rising and the second falling edge as will all
the remaining bits. The data may be captured on either
edge. The largest hold time margin is achieved if data is
captured on the rising edge of SCLK.
BUSY gives the end of conversion indication. When the
LTC1418 is configured as a master serial device, BUSY
can be used as a framing pulse and to three-state the
LTC1418
22
CLKOUT (= SCLK)
CS = EXT/INT = 0
BUSY (= RD)
CONVST
D
OUT
(SAMPLE N)
t
Hi-Z
6
t
10
U
D13
Figure 22. Internal Conversion Clock Selected. Data Transferred During Conversion Using
the ADC Clock Output as a Master Shift Clock (SCLK Driven from CLKOUT)
1
t
5
INFORMATION
D12
U
2
D11
3
(= SCLK)
CLKOUT
CONVST
D10
D
W
OUT
4
D9
24
5
D13
D8
CONVST
V
t
6
15
IL
t
14
U
LTC1418
DATA (N – 1)
D7
CS
RISING CLOCK
7
CAPTURE ON
CLKOUT
EXT/INT
25
t
CONV
BUSY
SCLK
D
OUT
RD
D6
8
26
18
19
20
HOLD
D12
23
17
D5
9
FALLING CLOCK
t
13
CLKOUT ( = SCLK)
CAPTURE ON
SCLK
D
OUT
BUSY (= RD)
D4
10
D
OUT
D3
11
D11
D2
12
(CONFIGURED
V
V
AS SLAVE)
REGISTER
P OR DSP
OH
OL
Figure 21. SCLK to D
D1
SHIFT
13
OR
1418 F22a
D0
14
15
ZEROS
FILL
16
OUT
t
D13
7
(SAMPLE N + 1)
V
t
Delay
SAMPLE
15
IL
t
t
14
8
Hi-Z
t
11
D13
1
DATA N
HOLD
D12
2
1418 F21
1418 F22b
D11
V
V
3
OH
OL