LTC1418IG Linear Technology, LTC1418IG Datasheet - Page 7

• Manufacturer Part Number: LTC1418IG
• Description: IC A/D CONV 14BIT SRL&PAR 28SSOP
• Manufacturer: Linear Technology

Specifications of LTC1418IG

• Number Of Bits: 14
• Sampling Rate (per Second): 200k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 21.5mW Unipolar; 31.5mW Bipolar
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

A
A
V
with 1 F.
REFCOMP (Pin 4): 4.096V Reference Bypass Pin.
Bypass to AGND with 10 F tantalum in parallel with 0.1 F
ceramic.
AGND (Pin 5): Analog Ground.
D13 to D6 (Pins 6 to 13): Three-State Data Outputs
(Parallel). D13 is the most significant bit.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
D5 (Pin 15): Three-State Data Output (Parallel).
D4 (EXTCLKIN) (Pin 16): Three-State Data Output
(Parallel). Conversion clock input (serial) when Pin 20
(EXT/INT) is tied high.
D3 (SCLK) (Pin 17): Three-State Data Output (Parallel).
Data clock input (serial).
D2 (CLKOUT) (Pin 18): Three-State Data Output (Parallel).
Conversion clock output (serial).
D1 (D
Serial data output (serial).
D0 (EXT/INT) (Pin 20): Three-State Data Output (Parallel).
Conversion clock selector (serial). An input low enables
TEST CIRCUITS
PIN
IN
IN
REF
DBN
U
+
–
A) HI-Z TO V
(Pin 1): Positive Analog Input.
(Pin 2): Negative Analog Input.
(Pin 3): 2.50V Reference Output. Bypass to AGND
OUT
FUNCTIONS
) (Pin 19): Three-State Data Output (Parallel).
U
1k
OH
DGND
AND V
Load Circuits for Access Timing
OL
TO V
U
C
OH
L
DBN
B) HI-Z TO V
OL
5V
AND V
1k
DGND
C
L
OH
TO V
1418 TC01
OL
the internal conversion clock. An input high indicates an
external conversion clock will be assigned to Pin 16
(EXTCLKIN).
SER/PAR (Pin 21): Data Output Mode.
SHDN (Pin 22): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by CS. CS = 0 for nap
mode and CS = 1 for sleep mode.
RD (Pin 23): Read Input. This enables the output drivers
when CS is low.
CONVST (Pin 24): Conversion Start Signal. This active low
signal starts a conversion on its falling edge.
CS (Pin 25): Chip Select. This input must be low for the
ADC to recognize the CONVST and RD inputs. CS also sets
the shutdown mode when SHDN goes low. CS and SHDN
low select the quick wake-up nap mode. CS high and
SHDN low select sleep mode.
BUSY (Pin 26): The BUSY Output Shows the Converter
Status. It is low when a conversion is in progress.
V
Bypass to AGND with 10 F tantalum in parallel with 0.1 F
ceramic. Analog ground for unipolar operation.
V
10 F tantalum in parallel with 0.1 F ceramic.
SS
DD
DBN
(Pin 27): Negative Supply, – 5V for Bipolar Operation.
(Pin 28): 5V Positive Supply. Bypass to AGND with
A) V
Load Circuits for Output Float Delay
1k
OH
TO HI-Z
30pF
DBN
B) V
LTC1418
OL
5V
TO HI-Z
1k
1418 TC02
30pF
7