LTC1418IG Linear Technology, LTC1418IG Datasheet - Page 4

• Manufacturer Part Number: LTC1418IG
• Description: IC A/D CONV 14BIT SRL&PAR 28SSOP
• Manufacturer: Linear Technology

Specifications of LTC1418IG

• Number Of Bits: 14
• Sampling Rate (per Second): 200k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 21.5mW Unipolar; 31.5mW Bipolar
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC1418
TI I G CHARACTERISTICS
The
temperature range; all other limits and typicals T
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below V
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V
Note 4: When these pin voltages are taken below V
by internal diodes. This product can handle input currents greater than
100mA below V
Note 5: V
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended input with A
4
SYMBOL
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
f
t
t
t
t
t
SAMPLE(MAX)
CONV
ACQ
ACQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
EXTCLKIN
dEXTCLKIN
H SCLK
L SCLK
H EXTCLKIN
L EXTCLKIN
W U
+ t
denotes specifications which apply over the full operating
CONV
DD
= 5V, V
SS
PARAMETER
Maximum Sampling Frequency
Conversion Time
Acquisition Time
Acquisition Plus Conversion Time
CS to RD Setup Time
CS to CONVST Setup Time
CS to SHDN Setup Time to Ensure Nap Mode
SHDN to CONVST Wake-Up Time from Nap Mode
CONVST Low Time
CONVST to BUSY Delay
Data Ready Before BUSY
Delay Between Conversions
Wait Time RD After BUSY
Data Access Time After RD
Bus Relinquish Time
RD Low Time
CONVST High Time
Delay Time, SCLK to D
Time from Previous Data Remain Valid After SCLK
Shift Clock Frequency
External Conversion Clock Frequency
Delay Time, CONVST to External Conversion Clock Input
SCLK High Time
SCLK Low Time
EXTCLKIN High Time
EXTCLKIN Low Time
without latchup. These pins are not clamped to V
IN
SS
–
grounded.
= 0V or – 5V, f
SS
or above V
SAMPLE
OUT
CC
= 200kHz, t
Valid
without latchup.
A
= 25 C.
SS
SS
they will be clamped
or above V
r
= t
f
= 5ns unless
(Note 5)
DD
, they
DD
.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB
when the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling edge of CONVST starts a conversion. If CONVST
returns high at a critical point during the conversion, it can create small
errors. For best performance ensure that CONVST returns high either
within 2.1 s after the conversion starts or after BUSY rises.
Note 12: Pins 16 (D4/EXTCLKIN), 17 (D3/SCLK) and 20 (DO/EXT/INT) at
0V or 5V. See Power Shutdown.
CONDITIONS
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Note 10)
(Notes 10, 11)
CL = 25pF
(Note 10)
C
C
Commercial
Industrial
C
C
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
L
L
L
L
= 25pF
= 100pF
= 25pF (Note 9)
= 25pF (Note 9)
MIN
0.03
200
500
– 5
t
40
40
40
20
15
40
15
10
20
10
0
0
TYP
500
250
250
3.4
0.3
3.7
35
35
15
20
35
25
8
MAX
12.5
533
4.5
70
30
40
40
55
20
25
30
70
4
1
5
UNITS
MHz
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s