DAC1005D650HW/C1,5 NXP Semiconductors, DAC1005D650HW/C1,5 Datasheet - Page 12

• Manufacturer Part Number: DAC1005D650HW/C1,5
• Description: IC DAC 10BIT 650MSPS DL 100HTQFP
• Manufacturer: NXP Semiconductors

Specifications of DAC1005D650HW/C1,5

• Settling Time: 20ns
• Number Of Bits: 10
• Data Interface: SPI™
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 1.4W
• Operating Temperature: -45°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286776518

NXP Semiconductors
Table 5.
V
T
unless otherwise specified.
[1]
[2]
[3]
[4]
DAC1005D650
Product data sheet
Symbol
SFDR
IMD3
ACPR
NSD
amb
DDA(1V8)
D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
CLKP and CLKN inputs are at differential LVDS levels. An external differential resistor with a value of between 80 Ω and 120 Ω should
be connected across the pins (see
|V
and the inductance between the receiver and the driver circuit ground.
IMD3 rejection with −6 dBFS/tone.
=
gpd
RBW
−
40
| represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance
= V
°
Characteristics
C to +85
DDD(1V8)
third-order
Parameter
restricted bandwidth
spurious-free dynamic
range
intermodulation
distortion
adjacent channel
power ratio
noise spectral density
= 1.8 V; V
°
C; typical values measured at T
…continued
DDA(3V3)
Figure
= V
Conditions
f
0 dBFS
f
f
Msps; f
f
Msps; f
f
Msps; f
f
f
s
f
s
data
data
data
s
o
s
8).
= 640 Msps; f
= 640 Msps; 8× interpolation
= 640 Msps; 8× interpolation;
All information provided in this document is subject to legal disclaimers.
2.51 MHz ≤ f
B = 30 kHz
2.71 MHz ≤ f
B = 30 kHz
3.51 MHz ≤ f
B = 30 kHz
4 MHz ≤ f
B = 1 MHz
f
f
f
f
1 carrier; B = 5 MHz
2 carriers; B = 10 MHz
4 carriers; B = 20 MHz
1 carrier; B = 5 MHz
2 carriers; B = 10 MHz
4 carriers; B = 20 MHz
1 carrier; B = 5 MHz
2 carriers; B = 10 MHz
4 carriers; B = 20 MHz
= 19 MHz at 0 dBFS
noise shaper disabled
noise shaper enabled
= 320 Msps; 4× interpolation
o1
o1
o1
o1
DD(IO)(3V3)
= 76.8 MHz; f
= 153.6 MHz; f
= 153.6 MHz; f
= 49 MHz; f
= 95 MHz; f
= 95 MHz; f
= 152 MHz; f
o
o
o
= 96 MHz
= 115.2 MHz
= 153.6 MHz
Rev. 2 — 3 September 2010
offset
Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
= 3.3 V; AGND, DGND and GNDIO shorted together;
amb
offset
offset
offset
o
≤ 40 MHz;
o2
o2
o2
= 96 MHz at
= 25
s
o2
s
s
≤ 2.71 MHz;
≤ 3.51 MHz;
= 51 MHz
= 97 MHz
= 97 MHz
= 614.4
≤ 4 MHz;
= 154 MHz C
= 614.4
= 614.4
°
C; R
L
= 50
Test
I
I
I
I
C
C
I
I
C
C
C
C
C
C
C
C
C
C
Ω
; I
[1]
O(fs)
[4]
[4]
[4]
[4]
= 20 mA; maximum sample rate; PLL on;
Min
-
-
-
-
-
-
67
-
-
-
-
-
-
-
-
-
-
-
-
DAC1005D650
Typ
−89
−88
−89
−83
81
80
79
77
64
61
60
67
63
60
65
63
60
−138 -
−139 -
Max
−83
-
−81
−67
-
-
-
-
-
-
-
-
-
-
-
-
-
© NXP B.V. 2010. All rights reserved.
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBm/Hz
dBm/Hz
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