DAC1005D650HW/C1,5 NXP Semiconductors, DAC1005D650HW/C1,5 Datasheet - Page 30

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DAC1005D650HW/C1,5

Manufacturer Part Number
DAC1005D650HW/C1,5
Description
IC DAC 10BIT 650MSPS DL 100HTQFP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of DAC1005D650HW/C1,5

Settling Time
20ns
Number Of Bits
10
Data Interface
SPI™
Number Of Converters
2
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
1.4W
Operating Temperature
-45°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935286776518

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DAC1005D650HW/C1,5
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NXP Semiconductors
DAC1005D650
Product data sheet
10.12 Analog output
Table 38.
Default settings are shown highlighted.
The DAC1005D650 has two output channels each of which produces two complementary
current outputs. These allow the even-order harmonics and noise to be reduced. The pins
are IOUTAP/IOUTAN and IOUTBP/IOUTBN respectively and need to be connected using
a load resistor R
Refer to
of a parallel combination of NMOS current sources, and their associated switches, for
each segment.
The cascode source configuration increases the output impedance of the source, thus
improving the dynamic performance of the DAC by introducing less distortion.
The device can provide an output level of up to 2 V
following stages and the targeted performances.
DAC_OFFSET[8:0]
Decimal
−256
−255
...
−1
0
+1
...
+254
+255
Fig 12. Equivalent analog output circuit (one DAC)
Figure 12
Digital offset adjustment
All information provided in this document is subject to legal disclaimers.
L
to the 3.3 V analog power supply (V
for the equivalent analog output circuit of one DAC. This circuit consists
Rev. 2 — 3 September 2010
Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
AGND
Two’s complement
1 0000 0000
1 0000 0001
...
1 1111 1111
0 0000 0000
0 0000 0001
...
0 1111 1110
0 1111 1111
AGND
IOUTAP/IOUTBP
IOUTAN/IOUTBN
o(p-p)
DDA(3V3)
depending on the application, the
DAC1005D650
Offset applied
−256
−255
...
−1
0
+1
...
+254
+255
V
).
DDA(3V3)
R L
001aah019
R L
© NXP B.V. 2010. All rights reserved.
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