DAC1005D650HW/C1,5 NXP Semiconductors, DAC1005D650HW/C1,5 Datasheet - Page 21

• Manufacturer Part Number: DAC1005D650HW/C1,5
• Description: IC DAC 10BIT 650MSPS DL 100HTQFP
• Manufacturer: NXP Semiconductors

Specifications of DAC1005D650HW/C1,5

• Settling Time: 20ns
• Number Of Bits: 10
• Data Interface: SPI™
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 1.4W
• Operating Temperature: -45°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286776518

NXP Semiconductors
DAC1005D650
Product data sheet
10.3.1 Dual-port mode
10.3.2 Interleaved mode
10.3 Input data
Table 28.
Table 29.
Default settings are shown highlighted.
The setting applied to MODE_SEL (register 00h[3]; see
whether the DAC1005D650 operates in the Dual-port mode or in the Interleaved mode
(see
Table 30.
The data input for Dual-port mode operation is shown in
DAC has its own independent data input. The data enters the input latch on the rising
edge of the internal clock signal and is transferred to the DAC latch.
The data input for Interleaved mode operation is shown in
operation”.
Bit
7 to 0
Bit
7
1 to 0
Bit 3 setting
0
1
Fig 5.
Table
Symbol
AUX_B[9:2]
Symbol
AUX_B_PD
AUX_B[1:0]
n in Qn = 0 to 9 and for In is 0 to 9.
Dual-port mode
DAC_B_Aux_MSB register (address 1Ch) bit description
DAC_B_Aux_LSB register (address 1Dh) bit description
Mode selection
30).
All information provided in this document is subject to legal disclaimers.
Function
Dual-port mode (pin Q9)
Interleaved mode (pin SELIQ) active
Qn
In
Rev. 2 — 3 September 2010
Access
R/W
Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
LATCH
LATCH
Q
I
Value
-
R/W
Access Value
R/W
2 ×
2 ×
FIR 1
FIR 1
Description
most significant 8 bits for the auxiliary DAC B
0
1
I9 to I0
active
2 ×
2 ×
FIR 2
FIR 2
Description
auxiliary DAC B power
lower 2 bits for the auxiliary DAC B
on
off
Table 10 on page
Figure 5 “Dual-port
Figure 6 “Interleaved mode
DAC1005D650
2 ×
2 ×
FIR 3
FIR 3
001aaj585
Q9 to Q0
active
off
© NXP B.V. 2010. All rights reserved.
17) defines
mode”. Each
21 of 42