DAC1005D650HW/C1,5 NXP Semiconductors, DAC1005D650HW/C1,5 Datasheet - Page 24

• Manufacturer Part Number: DAC1005D650HW/C1,5
• Description: IC DAC 10BIT 650MSPS DL 100HTQFP
• Manufacturer: NXP Semiconductors

Specifications of DAC1005D650HW/C1,5

• Settling Time: 20ns
• Number Of Bits: 10
• Data Interface: SPI™
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 1.4W
• Operating Temperature: -45°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286776518

NXP Semiconductors
DAC1005D650
Product data sheet
Table 31.
The settings applied to PLL_PHASE[1:0] (register 02h[2:1]) and PLL_POL
(register 02h[0]), allows adjustment of the phase and polarity of the sampling clock. This
occurs at the input of the DAC core and depends mainly on the sampling frequency. Some
examples are given in
Table 32.
Mode
Dual-port
Dual-port
Dual-port
Interleaved
Interleaved
Interleaved
Mode
Dual-port
Dual-port
Dual-port
Interleaved
Interleaved
Interleaved
Frequencies
Sample clock phase and polarity examples
All information provided in this document is subject to legal disclaimers.
CLK input
(MHz)
160
160
80
320
320
160
Input data rate
(MHz)
80
80
80
160
160
160
Rev. 2 — 3 September 2010
Table 32 “Sample clock phase and polarity
Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
Input data rate
(MHz)
160
160
80
320
320
160
Interpolation
2×
4×
8×
2×
4×
8×
Interpolation
2×
4×
8×
2×
4×
8×
Update rate
(Msps)
160
320
640
160
320
640
DAC1005D650
Update rate
(Msps)
320
640
640
320
640
640
PLL_PHASE
[1:0]
01
01
01
01
01
01
examples”.
© NXP B.V. 2010. All rights reserved.
PLL_DIV[1:0]
01 (/4)
01 (/4)
10 (/8)
00 (/2)
00 (/2)
01 (/4)
PLL_POL
1
0
1
1
0
1
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