DAC1005D650HW/C1,5 NXP Semiconductors, DAC1005D650HW/C1,5 Datasheet - Page 39

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DAC1005D650HW/C1,5

Manufacturer Part Number
DAC1005D650HW/C1,5
Description
IC DAC 10BIT 650MSPS DL 100HTQFP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of DAC1005D650HW/C1,5

Settling Time
20ns
Number Of Bits
10
Data Interface
SPI™
Number Of Converters
2
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
1.4W
Operating Temperature
-45°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935286776518

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DAC1005D650HW/C1,5
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NXP Semiconductors
13. Glossary
14. Revision history
Table 42.
DAC1005D650
Product data sheet
Document ID
DAC1005D650 v2.0
Modifications
DAC1005D650 v1.0
Revision history
Spurious-Free Dynamic Range (SFDR): — The ratio between the RMS value of the
reconstructed output sine wave and the RMS value of the largest spurious observed
(harmonic and non-harmonic, excluding DC component) in the frequency domain.
Intermodulation Distortion (IMD): — From a dual-tone digital input sine wave (these
two frequencies being close together), the intermodulation distortion products IMD2 and
IMD3 (respectively, 2
IMD2 — The ratio of the RMS value of either tone to the RMS value of the worst 2
intermodulation product.
IMD3 — The ratio of the RMS value of either tone to the RMS value of the worst 3
intermodulation product.
Restricted Bandwidth Spurious-Free Dynamic Range — The ratio of the RMS value of
the reconstructed output sine wave to the RMS value of the noise, including the
harmonics, in a given bandwidth centered around f
Release date
20100903
20090728
Figure 18
All information provided in this document is subject to legal disclaimers.
corrected the value of the resistors on pin AUXnP
Data sheet status
Product data sheet
Product data sheet
nd
Rev. 2 — 3 September 2010
and 3
Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
rd
order components) are defined below.
Change notice
-
-
offset
.
DAC1005D650
Supersedes
DAC1005D650 v1.0
-
© NXP B.V. 2010. All rights reserved.
nd
rd
39 of 42
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